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| author | Marc Jones <marc.jones@se-eng.com> | 2015-09-15 23:05:00 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-10 00:25:14 +0100 |
| commit | 3b0a626edc9d1a45324fd8e77b10e4e49155bb8f (patch) | |
| tree | 75a7a0fc8084031da63f3aa3e37448ecb7d5cb54 /src/mainboard/intel/stargo2/dsdt.asl | |
| parent | 2d72345f80266555aa3c358d0b7bcda083687b5c (diff) | |
| download | coreboot-3b0a626edc9d1a45324fd8e77b10e4e49155bb8f.tar.xz | |
mainboard/intel: Add Stargo2
The Intel Stargo2 is a communications device reference design.
This mainboard uses the Sandy/Ivy Bridge and is paired with
the i89xx southbridge. The FSP package is available from Intel:
https://intel.com/fsp.
Change-Id: I75c527f0eb0de1ee6ac13d8d276d7cf23b5b120c
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12170
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/stargo2/dsdt.asl')
| -rw-r--r-- | src/mainboard/intel/stargo2/dsdt.asl | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/mainboard/intel/stargo2/dsdt.asl b/src/mainboard/intel/stargo2/dsdt.asl new file mode 100644 index 0000000000..73ba53998d --- /dev/null +++ b/src/mainboard/intel/stargo2/dsdt.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + #include <southbridge/intel/fsp_i89xx/acpi/platform.asl> + + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/fsp_i89xx/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include <cpu/intel/fsp_model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/fsp_i89xx/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/fsp_i89xx/acpi/sleepstates.asl> +} |