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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-05-01 10:34:54 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-17 20:18:34 +0200 |
| commit | 5cb9ddad3e8d487945c4a1e4b82575369b08be52 (patch) | |
| tree | fb75b15795c3b6608f6131de31600cc6b0da24a9 /src/mainboard/intel/strago/Kconfig | |
| parent | b18f522bced85deda8a339cdf9aa310478db3a71 (diff) | |
| download | coreboot-5cb9ddad3e8d487945c4a1e4b82575369b08be52.tar.xz | |
mainboard/intel: Add Braswell based Strago board
Add the initial files to support the Intel RVP for Braswell.
Matches chromium tree at 927026db
This board uses the Braswell FSP 1.1 image and does not build without
the FspUpdVpd.h file.
BRANCH=none
BUG=None
TEST=Build and run ChromeOS on strago
Change-Id: I5cb2efe3d8adf919165c62b25e08c544b316a05a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10052
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/strago/Kconfig')
| -rwxr-xr-x | src/mainboard/intel/strago/Kconfig | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig new file mode 100755 index 0000000000..a7932e1923 --- /dev/null +++ b/src/mainboard/intel/strago/Kconfig @@ -0,0 +1,67 @@ +if BOARD_INTEL_STRAGO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ALWAYS_LOAD_OPROM + select BOARD_ROMSIZE_KB_8192 + select CHROMEOS + select CHROMEOS_VBNV_CMOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_MEC + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP + select EC_SOFTWARE_SYNC + select ENABLE_BUILTIN_COM1 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM + select SOC_INTEL_BRASWELL + select VBOOT_DYNAMIC_WORK_BUFFER + select VIRTUAL_DEV_SWITCH + select LID_SWITCH + + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory configuration data. + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory SPD data. +config DYNAMIC_VNN_SUPPORT + bool "Enables support for Dynamic VNN" + default n +config MAINBOARD_DIR + string + default intel/strago + +config MAINBOARD_PART_NUMBER + string + default "Strago" + +config MAINBOARD_VENDOR + string + default "Intel" + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 +config VBOOT_REFCODE_INDEX + hex + default 0x3 +if !CONFIG_GOP_SUPPORT +config VGA_BIOS_FILE + string + default "3rdparty/blobs/mainboard/intel/strago/vgabios_c0.bin" if C0_DISP_SUPPORT + default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" if !C0_DISP_SUPPORT +config VGA_BIOS_ID + string + default "8086,22b1" if C0_DISP_SUPPORT + default "8086,22b0" if !C0_DISP_SUPPORT +endif +endif # BOARD_INTEL_STRAGO |