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author | Divagar Mohandass <divagar.mohandass@intel.com> | 2015-09-08 15:03:45 +0530 |
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committer | Martin Roth <martinroth@google.com> | 2016-01-28 00:02:15 +0100 |
commit | 39f84fa6623f8981816682138d02acf3c31f3672 (patch) | |
tree | 4f95ac5c8d782b75cd9b902317d70c3f7fb7b593 /src/mainboard/intel/strago/romstage.c | |
parent | 4f4c6e88be48d62c41c88bc5b36828c967e0d6e4 (diff) | |
download | coreboot-39f84fa6623f8981816682138d02acf3c31f3672.tar.xz |
intel/strago: Clean up DDR configuration.
This change includes following changes:
- Clean up the DDR configuration and flow.
- Removing support for non LPDDR3 boards.
- Supporting only LPDDR3 and PMIC config.
TEST=Build/flash CB and boot the platform to OS.
Change-Id: I8369443da728a4c07e0c1a82040d94034c3542da
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297941
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13122
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/strago/romstage.c')
-rwxr-xr-x | src/mainboard/intel/strago/romstage.c | 26 |
1 files changed, 1 insertions, 25 deletions
diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index e582b56c2b..56ab9a7309 100755 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -25,32 +25,8 @@ #include "onboard.h" #include <boardid.h> -/* All FSP specific code goes in this block */ -void mainboard_romstage_entry(struct romstage_params *rp) -{ - struct pei_data *ps = rp->pei_data; - - mainboard_fill_spd_data(ps); - - /* Call back into chipset code with platform values updated. */ - romstage_common(rp); -} - void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - int id; - id = board_id(); - if (id == BOARD_BCRD2) { - memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - memory_params->PcdDvfsEnable = 0; - } else { - memory_params->PcdMemoryTypeEnable = MEM_DDR3; - memory_params->PcdMemorySpdPtr = - (u32)params->pei_data->spd_data_ch0; - memory_params->PcdMemChannel0Config = - params->pei_data->spd_ch0_config; - memory_params->PcdMemChannel1Config = - params->pei_data->spd_ch1_config; - } + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; } |