diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-03-23 23:41:53 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-27 03:03:16 +0200 |
| commit | 5029a1668e0ca99ac64210967e22c971b0395efa (patch) | |
| tree | f67df6c276760e91bdb49a4aab393b6894f81408 /src/mainboard/intel/strago | |
| parent | 3795b03b69129367d57c93033785d7877aabc2cc (diff) | |
| download | coreboot-5029a1668e0ca99ac64210967e22c971b0395efa.tar.xz | |
ec: Use EC_ENABLE_LID_SWITCH for all mainboards with LID using chromeec
Instead of defining a separate LID device for mainboards using
chromeec, define EC_ENABLE_LID_SWITCH for these boards.
Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18964
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/strago')
| -rw-r--r-- | src/mainboard/intel/strago/acpi/ec.asl | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/strago/acpi/mainboard.asl | 10 |
2 files changed, 3 insertions, 10 deletions
diff --git a/src/mainboard/intel/strago/acpi/ec.asl b/src/mainboard/intel/strago/acpi/ec.asl index f4ac2956bd..e023f3ba2b 100644 --- a/src/mainboard/intel/strago/acpi/ec.asl +++ b/src/mainboard/intel/strago/acpi/ec.asl @@ -17,5 +17,8 @@ /* mainboard configuration */ #include "ec.h" +/* Enable LID switch */ +#define EC_ENABLE_LID_SWITCH + /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl index 0353eede4e..17c83bf09e 100644 --- a/src/mainboard/intel/strago/acpi/mainboard.asl +++ b/src/mainboard/intel/strago/acpi/mainboard.asl @@ -19,16 +19,6 @@ Scope (\_SB) { - Device (LID0) - { - Name (_HID, EisaId ("PNP0C0D")) - Method (_LID, 0) - { - Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) - Return (\LIDS) - } - } - Device (PWRB) { Name (_HID, EisaId ("PNP0C0C")) |