diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 13:01:13 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:30:31 +0200 |
| commit | 30b0c7adf0a5d77a8e902dbbf0ee68954bf28385 (patch) | |
| tree | cd13a5a401a9a4698aa3e7601f1fd91567a0269a /src/mainboard/intel/strago | |
| parent | 95c4344a2092bd9fd5eca74d23d0c270628f66d2 (diff) | |
| download | coreboot-30b0c7adf0a5d77a8e902dbbf0ee68954bf28385.tar.xz | |
mainboards: align on using ACPI_Sx definitions
The mainboard_smi_sleep() function takes ACPI sleep values
of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure
that whatever hardware PM1 control register values are used
the interface to the mainboard is the same. Move all the
SMI handlers in the mainboard directory to not open code
the literal values 3 and 5 for ACPI_S3 and ACPI_S5.
There were a few notable exceptions where the code was
attempting to use the hardware values and not the common
translated values. The few users of SLEEP_STATE_X were
updated to align with ACPI_SX as those defines are
already equal. The removal of SLEEP_STATE_X defines is
forthcoming in a subsequent patch.
BUG=chrome-os-partner:54977
Change-Id: I76592c9107778cce5995e5af764760453f54dc50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15664
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel/strago')
| -rw-r--r-- | src/mainboard/intel/strago/smihandler.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index 0f77bf39ad..6cd01e2b33 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> @@ -100,7 +101,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) { /* Disable USB charging if required */ switch (slp_typ) { - case 3: + case ACPI_S3: #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) if (smm_get_gnvs()->s3u0 == 0) google_chromeec_set_usb_charge_mode( @@ -115,7 +116,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; - case 5: + case ACPI_S5: #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) if (smm_get_gnvs()->s5u0 == 0) google_chromeec_set_usb_charge_mode( @@ -140,7 +141,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) ; /* Set LPC lines to low power in S3/S5. */ - if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5)) + if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) lpc_set_low_power(); #endif } |