mb/intel/tglrvp: Add initial mainboard code

This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.

This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761

Below are the changes done over the copy patch:

 1. Rename "Icelake" with "Tigerlake".
 2. Replace "icelake_rvp" with "tglrvp".
 3. Rename "icl" with "tgl".
 4. Remove unwanted SPD file, add empty SPD as
    placeholder.
 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake".
 6. Empty romstage_fsp_params.c, to fill it later with
    SOC specific config.
 7. Empty GPIO configuration, to be filled as per board.
 8. Change copyright year to 2019.
 9. Add board support namely BOARD_INTEL_TGLRVP_UP3
 10. Replace icl_u and icl_y variant with tglrvp variant.
 11. Remove basebord gpio.c and rely on variant override.
 12. Remove HDA verb table and config support.

Changes to follow on top of this:
 1. Add correct memory parameters, add SPDs.
 2. Clean up devicetree as per tigerlake SOC.
 3. Add GPIO support.
 4. Update chromeos.fmd to make 32MB BIOS region.
 5. clean up and make empty devicetree setting

TEST=Build tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>

1 files changed, 57 insertions, 0 deletions

diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c
new file mode 100644
index 0000000000..372f6cefa2
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/chromeos.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_lid_switch(void)
+{
+	/* Lid always open */
+	return 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}
+
+int get_write_protect_state(void)
+{
+	/* No write protect */
+	return 0;
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	const struct cros_gpio *gpios;
+	size_t num;
+
+	gpios = variant_cros_gpios(&num);
+	chromeos_acpi_gpio_generate(gpios, num);
+}