soc/intel/tigerlake: Reorganize memory initialization support

This change reorganizes memory initialization code for LPDDR4x on
TGL to allow sharing of code when adding support for other memory
types. In follow-up changes, support for DDR4 will be added.

1. It adds configuration for memory topology which is currently only
MEMORY_DOWN, however DDR4 requires more topologies to be
supported.
2. spd_info structure is organized to allow mixed topologies as well.
3. DQ/DQS maps are organized to reflect hardware configuration.

TEST=Verified that volteer still boots and memory initialization is
successful.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>

1 files changed, 5 insertions, 4 deletions

diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c
index 0af394494f..d8057f6564 100644
--- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c
@@ -56,13 +56,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
 
-	const struct mb_lpddr4x_cfg *mem_config = variant_memory_params();
+	const struct lpddr4x_cfg *mem_config = variant_memory_params();
 	const struct spd_info spd_info = {
-		.read_type = READ_SPD_CBFS,
-		.spd_spec.spd_index = mainboard_get_spd_index(),
+		.topology = MEMORY_DOWN,
+		.md_spd_loc = SPD_CBFS,
+		.cbfs_index = mainboard_get_spd_index(),
 	};
 	bool half_populated = false;
 
-	meminit_lpddr4x_dimm0(mem_cfg, mem_config, &spd_info, half_populated);
+	meminit_lpddr4x(mem_cfg, mem_config, &spd_info, half_populated);
 
 }