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| author | John Zhao <john.zhao@intel.com> | 2020-08-18 22:32:47 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-21 07:52:39 +0000 |
| commit | 3af09bb16f19af2f455e592520cd7a3272391f9a (patch) | |
| tree | 11a4c40663f159a5c63678d9a004839dd7d223d2 /src/mainboard/intel/tglrvp | |
| parent | b728e2ccbc3e0523b01658df58cf9bcb91d7d173 (diff) | |
| download | coreboot-3af09bb16f19af2f455e592520cd7a3272391f9a.tar.xz | |
mb/intel/tglrvp: Disable TBT_PCIE3 for UP4
Tiger Lake External Design Specification (Document #575683) states UP4
TBT_PCIE3 is not applicable. Disable TC3 for UP4.
BUG=None
Test=Built UP4 image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Icff8fccf9ac29c315c2a4dd08a3ec8a8efe9c453
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44572
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index ccc4df89bb..a79bf80073 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -153,7 +153,7 @@ chip soc/intel/tigerlake device pci 07.0 on end # TBT_PCIe0 0x9A23 device pci 07.1 on end # TBT_PCIe1 0x9A25 device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 on end # TBT_PCIe3 0x9A29 + device pci 07.3 off end # TBT_PCIe3 0x9A29 device pci 08.0 off end # GNA 0x9A11 device pci 09.0 off end # NPK 0x9A33 device pci 0a.0 off end # Crash-log SRAM 0x9A0D |