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authorStefan Reinauer <stepan@coresystems.de>2010-04-09 13:33:59 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-09 13:33:59 +0000
commitd41a0bc532c837705d5abc2334e1bbf9dd06eb83 (patch)
tree9999b4b1d4f8b3f0e0cfb152d5ec7d6b4e3cca70 /src/mainboard/intel/truxton
parentaa987b23e4a639d1c6bfd6f3043a465874d56953 (diff)
downloadcoreboot-d41a0bc532c837705d5abc2334e1bbf9dd06eb83.tar.xz
Drop the need for cpu_reset, it's really just a short cut to stage2.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel/truxton')
-rw-r--r--src/mainboard/intel/truxton/romstage.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index 4163c873b0..41629ef557 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -58,6 +58,7 @@ static inline int spd_read_byte(u16 device, u8 address)
#include "northbridge/intel/i3100/raminit_ep80579.c"
#include "lib/generic_sdram.c"
#include "../../intel/jarrell/debug.c"
+#include "arch/i386/lib/stages.c"
/* #define TRUXTON_DEBUG */
@@ -77,7 +78,7 @@ static void main(unsigned long bist)
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (memory_initialized()) {
- asm volatile ("jmp __cpu_reset");
+ skip_romstage();
}
}