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| author | Stefan Reinauer <reinauer@chromium.org> | 2014-12-17 13:23:05 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2014-12-18 02:10:03 +0100 |
| commit | 61ed48c9233e0d74ef5c6847052662d075553691 (patch) | |
| tree | 175715f83a1dca3e5ce3c391801a2150b79805cf /src/mainboard/intel/truxton | |
| parent | 1882d65364fad35485dbe2069c23059c78320e3b (diff) | |
| download | coreboot-61ed48c9233e0d74ef5c6847052662d075553691.tar.xz | |
intel/truxton: Un-romcc-ify board
Change-Id: Iaf1756321960041f6a152d5dd4c9108291f51300
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7852
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/intel/truxton')
| -rw-r--r-- | src/mainboard/intel/truxton/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/truxton/romstage.c | 11 |
2 files changed, 2 insertions, 10 deletions
diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig index 5aa4b57cfd..11058e6097 100644 --- a/src/mainboard/intel/truxton/Kconfig +++ b/src/mainboard/intel/truxton/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I3100 select SUPERIO_INTEL_I3100 select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 960cccb8d6..0677cf6940 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -31,7 +31,6 @@ #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" #include "superio/intel/i3100/i3100.h" -#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "superio/intel/i3100/early_serial.c" #include "lib/debug.c" // XXX @@ -47,16 +46,12 @@ static inline int spd_read_byte(u16 device, u8 address) #include "northbridge/intel/i3100/raminit_ep80579.c" #include "lib/generic_sdram.c" -#include "../../intel/jarrell/debug.c" -#include "arch/x86/lib/stages.c" #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) #include <cpu/intel/romstage.h> -static void main(unsigned long bist) +void main(unsigned long bist) { - msr_t msr; - u16 perf; static const struct mem_controller mch[] = { { .node_id = 0, @@ -67,9 +62,8 @@ static void main(unsigned long bist) if (bist == 0) { /* Skip this if there was a built in self test failure */ - early_mtrr_init(); if (memory_initialized()) - skip_romstage(); + return; } /* Set up the console */ @@ -89,7 +83,6 @@ static void main(unsigned long bist) print_pci_devices(); #endif enable_smbus(); - dump_spd_registers(); sdram_initialize(ARRAY_SIZE(mch), mch); dump_pci_devices(); |