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authorArnaud Maye <arnaud.maye@4dsp.com>2009-08-28 20:42:21 +0000
committerMyles Watson <mylesgw@gmail.com>2009-08-28 20:42:21 +0000
commit5b1d51ba2e9ac22c7878cd5e8d9c51d8269bb76b (patch)
treee5d2a3440c5b62ba5c59ec94ea377a622568e100 /src/mainboard/intel/truxton
parent8b1c382cc083f391405c29b2c83892e74904e801 (diff)
downloadcoreboot-5b1d51ba2e9ac22c7878cd5e8d9c51d8269bb76b.tar.xz
This patch adds VGA and PS/2 Keyboard/mouse support to the already existing intel truxton (ep80579) dev board.
This patch tries to improve the pcie portA configuration. The Matrox G550e PCIe gfx card shipped along with the dev board is supported. Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel/truxton')
-rw-r--r--src/mainboard/intel/truxton/Config.lb13
-rw-r--r--src/mainboard/intel/truxton/Options.lb12
-rw-r--r--src/mainboard/intel/truxton/devicetree.cb13
3 files changed, 37 insertions, 1 deletions
diff --git a/src/mainboard/intel/truxton/Config.lb b/src/mainboard/intel/truxton/Config.lb
index 7ec2da81b6..a297da1133 100644
--- a/src/mainboard/intel/truxton/Config.lb
+++ b/src/mainboard/intel/truxton/Config.lb
@@ -143,6 +143,19 @@ chip northbridge/intel/i3100
io 0x60 = 0x2f8
irq 0x70 = 3
end
+ end
+ chip superio/smsc/smscsuperio
+ device pnp 2e.0 off end
+ device pnp 2e.3 off end
+ device pnp 2e.4 off end
+ device pnp 2e.5 off end
+ device pnp 2e.7 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 2e.a off end
end
end
device pci 1f.2 on end # SATA
diff --git a/src/mainboard/intel/truxton/Options.lb b/src/mainboard/intel/truxton/Options.lb
index 2f98066cd3..2dd7db55fa 100644
--- a/src/mainboard/intel/truxton/Options.lb
+++ b/src/mainboard/intel/truxton/Options.lb
@@ -37,6 +37,7 @@ uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_LB_MEM_TOPK
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
@@ -67,6 +68,7 @@ uses CC
uses HOSTCC
uses CONFIG_CROSS_COMPILE
uses CONFIG_OBJCOPY
+uses CONFIG_CONSOLE_VGA
###
@@ -155,7 +157,12 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
##
## coreboot C code runs at this location in RAM
##
-default CONFIG_RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00100000
+
+##
+## in order to have coreboot running at 0x100000, TOPK has to be set
+##
+default CONFIG_LB_MEM_TOPK = 2*1024*1024
##
## Load the payload from the ROM
@@ -202,6 +209,9 @@ default CONFIG_TTYS0_BASE=0x3f8
# This defaults to 8 data bits, 1 stop bit, and no parity
default CONFIG_TTYS0_LCS=0x3
+# Enable the VGA console.
+default CONFIG_CONSOLE_VGA=1
+
##
### Select the coreboot loglevel
##
diff --git a/src/mainboard/intel/truxton/devicetree.cb b/src/mainboard/intel/truxton/devicetree.cb
index 7604beafe5..a21c2f4eae 100644
--- a/src/mainboard/intel/truxton/devicetree.cb
+++ b/src/mainboard/intel/truxton/devicetree.cb
@@ -26,6 +26,19 @@ chip northbridge/intel/i3100
io 0x60 = 0x2f8
irq 0x70 = 3
end
+ end
+ chip superio/smsc/smscsuperio
+ device pnp 2e.0 off end
+ device pnp 2e.3 off end
+ device pnp 2e.4 off end
+ device pnp 2e.5 off end
+ device pnp 2e.7 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 2e.a off end
end
end
device pci 1f.2 on end # SATA