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authorStefan Reinauer <stefan.reinauer@coreboot.org>2016-02-24 14:01:59 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2016-03-13 02:22:39 +0100
commit2510e2aa448dd7eb52232fa65def0be16af5da84 (patch)
treefbf906ed0261767fb6f0ff6a18a8e3f37cc1a392 /src/mainboard/intel/truxton
parente3fd63f264e1f6e2869cf5868e1810dff5641147 (diff)
downloadcoreboot-2510e2aa448dd7eb52232fa65def0be16af5da84.tar.xz
northbridge/intel/i3100: Unify UDELAY selection
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i3100 boards in the chipset. Change-Id: Ia66a0561c75777a9e98bb87117859808a2ff3732 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13786 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/truxton')
-rw-r--r--src/mainboard/intel/truxton/Kconfig1
-rw-r--r--src/mainboard/intel/truxton/romstage.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig
index 11058e6097..cd8e478f1b 100644
--- a/src/mainboard/intel/truxton/Kconfig
+++ b/src/mainboard/intel/truxton/Kconfig
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_HARD_RESET
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select UDELAY_TSC
select BOARD_ROMSIZE_KB_2048
config MAINBOARD_DIR
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index c637d24192..3ea65426d9 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -21,7 +21,6 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-#include "drivers/pc80/udelay_io.c"
#include <console/console.h>
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"