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authorDuncan Laurie <dlaurie@chromium.org>2013-07-19 08:48:05 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 07:38:42 +0100
commit3d299c4b092d3464ea90ddc338f62b04a61e0c46 (patch)
treea50c3cbd00e3d28b800e0ce82a0b573ff8f3dabb /src/mainboard/intel/wtm2
parent80fd5c4461041508a9579d698ab89dd97ec2ae15 (diff)
downloadcoreboot-3d299c4b092d3464ea90ddc338f62b04a61e0c46.tar.xz
lynxpoint me: add support for mbp clear wait in finalize step
The management engine is slow, requiring at least 500ms between when the Dram Init Done message is sent (right after memory training) to when the MBP will report that it is successfully cleared and that the ME can finally be sent the EOP message. Currently this is adding 100-150ms to the boot time. If we defer waiting for the MBP Clear indicator until the finalize step we can gain back that lost time. boot on falco with SMI debugging enabled to ensure that the ME is locked down in the finalize step: Finalizing Coreboot SMI# #0 SMI_STS: PM1 APM ME: MBP cleared ME: mkhi_end_of_post ME: END OF POST message successful (0) Change-Id: Icab4c8c8e00eea67bed5e8154d91a1eb48a492d1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62633 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4375 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/intel/wtm2')
-rw-r--r--src/mainboard/intel/wtm2/mainboard_smi.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c
index 3ffc68441d..bcc94d6f2b 100644
--- a/src/mainboard/intel/wtm2/mainboard_smi.c
+++ b/src/mainboard/intel/wtm2/mainboard_smi.c
@@ -60,7 +60,6 @@ int mainboard_smi_apmc(u8 apmc)
return 0;
}
- intel_me_finalize_smm();
intel_pch_finalize_smm();
intel_northbridge_haswell_finalize_smm();
intel_cpu_haswell_finalize_smm();