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authorAaron Durbin <adurbin@chromium.org>2013-06-13 17:29:36 -0700
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-12-01 23:27:10 +0100
commitc7633f4f5e3693c005791006e6cc788b218770c7 (patch)
treea03a6c4092bbfada0a0c1fbaafb7a3a516a1292e /src/mainboard/intel/wtm2
parent752b1e6d5d341e9c328d596a6f00bd8071274a48 (diff)
downloadcoreboot-c7633f4f5e3693c005791006e6cc788b218770c7.tar.xz
slippy/falco/peppy: Fix SPD GPIO initialization.
SPD GPIOs were being read prior to initialization in romstage_common. To fix, pass the copy_spd function to romstage_common, to be called at the appropriate time (after PCH init, before DRAM init). Change-Id: I2554813e56a58c8c81456f1a53cc8ce9c2030a73 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58608 Reviewed-on: http://review.coreboot.org/4237 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel/wtm2')
-rw-r--r--src/mainboard/intel/wtm2/romstage.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c
index f38389c543..0a24e48ba4 100644
--- a/src/mainboard/intel/wtm2/romstage.c
+++ b/src/mainboard/intel/wtm2/romstage.c
@@ -19,6 +19,7 @@
*/
#include <stdint.h>
+#include <stddef.h>
#include <console/console.h>
#include "cpu/intel/haswell/haswell.h"
#include "northbridge/intel/haswell/haswell.h"
@@ -123,6 +124,7 @@ void mainboard_romstage_entry(unsigned long bist)
.gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0],
.bist = bist,
+ .copy_spd = NULL,
};
/* Call into the real romstage main with this board's attributes. */