diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-05-07 13:28:56 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-25 23:27:09 +0100 |
| commit | 0e939155a332c884b2a068da6a9fc89246c34cb7 (patch) | |
| tree | 12db36839c5ce55ac5edbd47f0a4fbb34b73faa4 /src/mainboard/intel/wtm2 | |
| parent | 8a0cb8de65572d6cb40cd36f06fa2567953eb390 (diff) | |
| download | coreboot-0e939155a332c884b2a068da6a9fc89246c34cb7.tar.xz | |
wtm2: Set SerialIO I2C ports to 3.3V
These are both pulled up to 3.3V in the schematic.
Change-Id: I12e055a39ff6100300c3d285899b8d6239e3773d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50356
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4164
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel/wtm2')
| -rw-r--r-- | src/mainboard/intel/wtm2/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 31933690bf..2790cb9613 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -52,8 +52,8 @@ chip northbridge/intel/haswell register "sata_port_map" = "0x2" register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "1" # 1.8V - register "sio_i2c1_voltage" = "1" # 1.8V + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V device pci 13.0 on end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI |