wtm2: Convert to use soc/intel/broadwell

Convert wtm2 board to use the broadwell soc chipset.

BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2 with haswell and broadwell
CQ-DEPEND=CL:201067
CQ-DEPEND=CL:*164226

Original-Change-Id: Ifb0db15cc23a3b66430b32b2ad3f8ab2fb03c4c3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201070
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e1073c6e34ab2d436faf46dde5f6b3bf99692866)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I925b91a8de980b1768f03eaee915a7fd91fbdbda
Reviewed-on: http://review.coreboot.org/8001
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

14 files changed, 273 insertions, 588 deletions

diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig
index c868e73abd..7b4565f2eb 100644
--- a/src/mainboard/intel/wtm2/Kconfig
+++ b/src/mainboard/intel/wtm2/Kconfig
@@ -2,10 +2,7 @@ if BOARD_INTEL_WTM2
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select CPU_INTEL_SOCKET_RPGA989
-	select NORTHBRIDGE_INTEL_HASWELL
-	select SOUTHBRIDGE_INTEL_LYNXPOINT
-	select INTEL_LYNXPOINT_LP
+	select SOC_INTEL_BROADWELL
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
@@ -16,6 +13,16 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MONOTONIC_TIMER_MSR
 	select INTEL_INT15
 
+	select CHROMEOS_RAMOOPS_DYNAMIC
+
+config VBOOT_RAMSTAGE_INDEX
+	hex
+	default 0x1
+
+config VBOOT_REFCODE_INDEX
+	hex
+	default 0x2
+
 config MAINBOARD_DIR
 	string
 	default intel/wtm2
@@ -24,9 +31,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "WHITETIP MOUNTAIN 2"
 
-config MMCONF_BASE_ADDRESS
-	hex
-	default 0xf0000000
 
 config MAX_CPUS
 	int
diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc
index e519bb2caa..cbd993e691 100644
--- a/src/mainboard/intel/wtm2/Makefile.inc
+++ b/src/mainboard/intel/wtm2/Makefile.inc
@@ -24,3 +24,6 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += graphics.c
 ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+
+romstage-y += pei_data.c
+ramstage-y += pei_data.c
diff --git a/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl b/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl
deleted file mode 100644
index d91f9a42fd..0000000000
--- a/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for IvyBridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, 0, 16 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, 0, 22 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, 0, 17 },
-			Package() { 0x001cffff, 1, 0, 18 },
-			Package() { 0x001cffff, 2, 0, 19 },
-			Package() { 0x001cffff, 3, 0, 20 },
-			// EHCI	  			0:1d.0
-			Package() { 0x001dffff, 0, 0, 19 },
-			// XHCI	  			0:14.0
-			Package() { 0x0014ffff, 0, 0, 16 },
-			// LPC devices			0:1f.0
-			Package() { 0x001fffff, 0, 0, 21 },
-			Package() { 0x001fffff, 1, 0, 22 },
-			Package() { 0x001fffff, 2, 0, 23 },
-			Package() { 0x001fffff, 3, 0, 16 },
-			// Serial IO                    0:15.0
-			Package() { 0x0015ffff, 0, 0, 16 },
-			Package() { 0x0015ffff, 1, 0, 17 },
-			Package() { 0x0015ffff, 2, 0, 18 },
-			Package() { 0x0015ffff, 3, 0, 19 },
-			// SDIO                         0:17.0
-			Package() { 0x0017ffff, 0, 0, 16 },
-		})
-	} Else {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
-			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
-			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
-			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
-		})
-	}
-}
diff --git a/src/mainboard/intel/wtm2/acpi/thermal.asl b/src/mainboard/intel/wtm2/acpi/thermal.asl
index 36310e473e..7a15302f5c 100644
--- a/src/mainboard/intel/wtm2/acpi/thermal.asl
+++ b/src/mainboard/intel/wtm2/acpi/thermal.asl
@@ -18,6 +18,7 @@
  */
 
 // Thermal Zone
+#include "../thermal.h"
 
 Scope (\_TZ)
 {
@@ -68,41 +69,41 @@ Scope (\_TZ)
 
 		Method (_AC0) {
 			If (LLessEqual (\FLVL, 0)) {
-				Return (CTOK (\F0OF))
+				Return (CTOK (FAN0_THRESHOLD_OFF))
 			} Else {
-				Return (CTOK (\F0ON))
+				Return (CTOK (FAN0_THRESHOLD_ON))
 			}
 		}
 
 		Method (_AC1) {
 			If (LLessEqual (\FLVL, 1)) {
-				Return (CTOK (\F1OF))
+				Return (CTOK (FAN1_THRESHOLD_OFF))
 			} Else {
-				Return (CTOK (\F1ON))
+				Return (CTOK (FAN1_THRESHOLD_ON))
 			}
 		}
 
 		Method (_AC2) {
 			If (LLessEqual (\FLVL, 2)) {
-				Return (CTOK (\F2OF))
+				Return (CTOK (FAN2_THRESHOLD_OFF))
 			} Else {
-				Return (CTOK (\F2ON))
+				Return (CTOK (FAN2_THRESHOLD_ON))
 			}
 		}
 
 		Method (_AC3) {
 			If (LLessEqual (\FLVL, 3)) {
-				Return (CTOK (\F3OF))
+				Return (CTOK (FAN3_THRESHOLD_OFF))
 			} Else {
-				Return (CTOK (\F3ON))
+				Return (CTOK (FAN3_THRESHOLD_ON))
 			}
 		}
 
 		Method (_AC4) {
 			If (LLessEqual (\FLVL, 4)) {
-				Return (CTOK (\F4OF))
+				Return (CTOK (FAN4_THRESHOLD_OFF))
 			} Else {
-				Return (CTOK (\F4ON))
+				Return (CTOK (FAN4_THRESHOLD_ON))
 			}
 		}
 
diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c
index 20814ab676..b6c0f9aeef 100644
--- a/src/mainboard/intel/wtm2/acpi_tables.c
+++ b/src/mainboard/intel/wtm2/acpi_tables.c
@@ -29,67 +29,26 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/msr.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
+#include <broadwell/acpi.h>
+#include <broadwell/nvs.h>
 #include "thermal.h"
 
-static void acpi_update_thermal_table(global_nvs_t *gnvs)
-{
-	gnvs->f4of = FAN4_THRESHOLD_OFF;
-	gnvs->f4on = FAN4_THRESHOLD_ON;
-	gnvs->f4pw = FAN4_PWM;
-
-	gnvs->f3of = FAN3_THRESHOLD_OFF;
-	gnvs->f3on = FAN3_THRESHOLD_ON;
-	gnvs->f3pw = FAN3_PWM;
-
-	gnvs->f2of = FAN2_THRESHOLD_OFF;
-	gnvs->f2on = FAN2_THRESHOLD_ON;
-	gnvs->f2pw = FAN2_PWM;
-
-	gnvs->f1of = FAN1_THRESHOLD_OFF;
-	gnvs->f1on = FAN1_THRESHOLD_ON;
-	gnvs->f1pw = FAN1_PWM;
-
-	gnvs->f0of = FAN0_THRESHOLD_OFF;
-	gnvs->f0on = FAN0_THRESHOLD_ON;
-	gnvs->f0pw = FAN0_PWM;
-
-	gnvs->tcrt = CRITICAL_TEMPERATURE;
-	gnvs->tpsv = PASSIVE_TEMPERATURE;
-	gnvs->tmax = MAX_TEMPERATURE;
-}
-
 void acpi_create_gnvs(global_nvs_t *gnvs)
 {
+	acpi_init_gnvs(gnvs);
+
 	/* Enable USB ports in S3 */
 	gnvs->s3u0 = 1;
-	gnvs->s3u1 = 1;
 
 	/* Disable USB ports in S5 */
 	gnvs->s5u0 = 0;
-	gnvs->s5u1 = 0;
 
 	/* TPM Present */
 	gnvs->tpmp = 1;
 
-	/* IGD Displays */
-	gnvs->ndid = 3;
-	gnvs->did[0] = 0x80000100;
-	gnvs->did[1] = 0x80000240;
-	gnvs->did[2] = 0x80000410;
-	gnvs->did[3] = 0x80000410;
-	gnvs->did[4] = 0x00000005;
-
-#if CONFIG_CHROMEOS
-	/* Emerald Lake has no EC (?) */
-	gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
-#endif
-
-	acpi_update_thermal_table(gnvs);
+	gnvs->tcrt = CRITICAL_TEMPERATURE;
+	gnvs->tpsv = PASSIVE_TEMPERATURE;
+	gnvs->tmax = MAX_TEMPERATURE;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
@@ -101,23 +60,5 @@ unsigned long acpi_fill_madt(unsigned long current)
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
 				2, IO_APIC_ADDR, 0);
 
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
-	// Not implemented
-	return current;
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
-	/* No NUMA, no SRAT */
-	return current;
+	return acpi_madt_irq_overrides(current);
 }
diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c
index 1461a156ab..fe469f74b3 100644
--- a/src/mainboard/intel/wtm2/chromeos.c
+++ b/src/mainboard/intel/wtm2/chromeos.c
@@ -22,7 +22,7 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <southbridge/intel/lynxpoint/pch.h>
+#include <broadwell/gpio.h>
 
 /* Compile-time settings for developer and recovery mode. */
 #define DEV_MODE_SETTING 1
diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb
index 2790cb9613..54b2bffd32 100644
--- a/src/mainboard/intel/wtm2/devicetree.cb
+++ b/src/mainboard/intel/wtm2/devicetree.cb
@@ -1,4 +1,4 @@
-chip northbridge/intel/haswell
+chip soc/intel/broadwell
 
 	# Enable DisplayPort 1 Hotplug with 6ms pulse
 	register "gpu_dp_d_hotplug" = "0x06"
@@ -9,80 +9,58 @@ chip northbridge/intel/haswell
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	device cpu_cluster 0 on
-		chip cpu/intel/socket_rPGA989
-			device lapic 0 on end
-		end
-		chip cpu/intel/haswell
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
+	register "pirqa_routing" = "0x8b"
+	register "pirqb_routing" = "0x8a"
+	register "pirqc_routing" = "0x8b"
+	register "pirqd_routing" = "0x8b"
+	register "pirqe_routing" = "0x80"
+	register "pirqf_routing" = "0x80"
+	register "pirqg_routing" = "0x80"
+	register "pirqh_routing" = "0x80"
 
-			register "c1_battery" = "2"	# ACPI(C1) = MWAIT(C1E)
-			register "c2_battery" = "9"	# ACPI(C2) = MWAIT(C7S)
-			register "c3_battery" = "12"	# ACPI(C3) = MWAIT(C10)
+	register "alt_gp_smi_en" = "0x0000"
+	register "gpe0_en_1" = "0x00000400"
+	register "gpe0_en_2" = "0x00000000"
+	register "gpe0_en_3" = "0x00000000"
+	register "gpe0_en_4" = "0x00000000"
 
-			register "c1_acpower" = "2"	# ACPI(C1) = MWAIT(C1E)
-			register "c2_acpower" = "9"	# ACPI(C2) = MWAIT(C7S)
-			register "c3_acpower" = "12"	# ACPI(C3) = MWAIT(C10)
-		end
-	end
+	register "sata_port_map" = "0x2"
+	register "sio_acpi_mode" = "1"
 
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
 	device domain 0 on
 		device pci 00.0 on end # host bridge
 		device pci 02.0 on end # vga controller
-
-		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
-			register "pirqa_routing" = "0x8b"
-			register "pirqb_routing" = "0x8a"
-			register "pirqc_routing" = "0x8b"
-			register "pirqd_routing" = "0x8b"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x80"
-
-			register "alt_gp_smi_en" = "0x0000"
-			register "gpe0_en_1" = "0x00000400"
-			register "gpe0_en_2" = "0x00000000"
-			register "gpe0_en_3" = "0x00000000"
-			register "gpe0_en_4" = "0x00000000"
-
-			register "ide_legacy_combined" = "0x0"
-			register "sata_ahci" = "0x1"
-			register "sata_port_map" = "0x2"
-
-			register "sio_acpi_mode" = "1"
-			register "sio_i2c0_voltage" = "0" # 3.3V
-			register "sio_i2c1_voltage" = "0" # 3.3V
-
-			device pci 13.0 on end # Smart Sound Audio DSP
-			device pci 14.0 on end # USB3 XHCI
-			device pci 15.0 on end # Serial I/O DMA
-			device pci 15.1 on end # I2C0
-			device pci 15.2 on end # I2C1
-			device pci 15.3 on end # GSPI0
-			device pci 15.4 on end # GSPI1
-			device pci 15.5 on end # UART0
-			device pci 15.6 on end # UART1
-			device pci 16.0 on end # Management Engine Interface 1
-			device pci 16.1 off end # Management Engine Interface 2
-			device pci 16.2 off end # Management Engine IDE-R
-			device pci 16.3 off end # Management Engine KT
-			device pci 17.0 on end # SDIO
-			device pci 19.0 on end # GbE
-			device pci 1b.0 on end # High Definition Audio
-			device pci 1c.0 on end # PCIe Port #1
-			device pci 1c.1 on end # PCIe Port #2
-			device pci 1c.2 on end # PCIe Port #3
-			device pci 1c.3 on end # PCIe Port #4
-			device pci 1c.4 on end # PCIe Port #5
-			device pci 1c.5 on end # PCIe Port #6
-			device pci 1d.0 on end # USB2 EHCI
-			device pci 1e.0 off end # PCI bridge
-			device pci 1f.0 on end # LPC bridge
-			device pci 1f.2 on end # SATA Controller
-			device pci 1f.3 on end # SMBus
-			device pci 1f.6 on end # Thermal
-		end
+		device pci 03.0 on end # mini-hd audio
+		device pci 13.0 off end # Smart Sound Audio DSP
+		device pci 14.0 on end # USB3 XHCI
+		device pci 15.0 on end # Serial I/O DMA
+		device pci 15.1 on end # I2C0
+		device pci 15.2 on end # I2C1
+		device pci 15.3 off end # GSPI0
+		device pci 15.4 off end # GSPI1
+		device pci 15.5 off end # UART0
+		device pci 15.6 off end # UART1
+		device pci 16.0 on end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT
+		device pci 17.0 off end # SDIO
+		device pci 19.0 off end # GbE
+		device pci 1b.0 on end # High Definition Audio
+		device pci 1c.0 on end # PCIe Port #1
+		device pci 1c.1 on end # PCIe Port #2
+		device pci 1c.2 on end # PCIe Port #3
+		device pci 1c.3 on end # PCIe Port #4
+		device pci 1c.4 on end # PCIe Port #5
+		device pci 1c.5 on end # PCIe Port #6
+		device pci 1d.0 off end # USB2 EHCI
+		device pci 1e.0 off end # PCI bridge
+		device pci 1f.0 on end # LPC bridge
+		device pci 1f.2 on end # SATA Controller
+		device pci 1f.3 on end # SMBus
+		device pci 1f.6 on end # Thermal
 	end
 end
diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl
index 112a47ab4a..b920cd458b 100644
--- a/src/mainboard/intel/wtm2/dsdt.asl
+++ b/src/mainboard/intel/wtm2/dsdt.asl
@@ -33,26 +33,32 @@ DefinitionBlock(
 	#include "acpi/platform.asl"
 
 	// global NVS and variables
-	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+	#include <soc/intel/broadwell/acpi/globalnvs.asl>
 
 	// General Purpose Events
 	//#include "acpi/gpe.asl"
 
-	#include "acpi/thermal.asl"
-
-	#include "../../../cpu/intel/haswell/acpi/cpu.asl"
+	// CPU
+	#include <soc/intel/broadwell/acpi/cpu.asl>
 
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <northbridge/intel/haswell/acpi/haswell.asl>
-			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+			#include <soc/intel/broadwell/acpi/systemagent.asl>
+			#include <soc/intel/broadwell/acpi/pch.asl>
 		}
 	}
 
+	// Thermal handler
+	#include "acpi/thermal.asl"
+
+	// Chrome OS specific
 	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
-	/* Chipset specific sleep states */
-	#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
+	// Chipset specific sleep states
+	#include <soc/intel/broadwell/acpi/sleepstates.asl>
+
+	// Mainboard specific
+	#include "acpi/mainboard.asl"
 }
diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c
index 7afbbfa698..a8811d2d56 100644
--- a/src/mainboard/intel/wtm2/fadt.c
+++ b/src/mainboard/intel/wtm2/fadt.c
@@ -18,20 +18,16 @@
  */
 
 #include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/pch.h>
+#include <broadwell/acpi.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = get_pmbase();
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
 	header->length = sizeof(acpi_fadt_t);
-	header->revision = 3;
+	header->revision = 5;
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
@@ -42,114 +38,12 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->model = 1;
 	fadt->preferred_pm_profile = PM_MOBILE;
 
-	fadt->sci_int = 0x9;
-	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
-	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0;
-
-	fadt->pm1a_evt_blk = pmbase;
-	fadt->pm1b_evt_blk = 0x0;
-	fadt->pm1a_cnt_blk = pmbase + 0x4;
-	fadt->pm1b_cnt_blk = 0x0;
-	fadt->pm2_cnt_blk = pmbase + 0x50;
-	fadt->pm_tmr_blk = pmbase + 0x8;
-	fadt->gpe0_blk = pmbase + 0x80;
-	fadt->gpe1_blk = 0;
-
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 32;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-	fadt->cst_cnt = 0;
-	fadt->p_lvl2_lat = 1;
-	fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 0;
-	fadt->day_alrm = 0xd;
-	fadt->mon_alrm = 0x00;
-	fadt->century = 0x00;
-	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
-
-	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
-			ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
-			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
-	fadt->reset_reg.space_id = 1;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0;
-
-	fadt->reset_value = 6;
 	fadt->x_firmware_ctl_l = (unsigned long)facs;
 	fadt->x_firmware_ctl_h = 0;
 	fadt->x_dsdt_l = (unsigned long)dsdt;
 	fadt->x_dsdt_h = 0;
 
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = pmbase;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 0;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 0;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 8;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	fadt->x_gpe0_blk.space_id = 0;
-	fadt->x_gpe0_blk.bit_width = 0;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = 0;
-	fadt->x_gpe0_blk.addrh = 0x0;
-
-	fadt->x_gpe1_blk.space_id = 1;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0x0;
-	fadt->x_gpe1_blk.addrh = 0x0;
+	acpi_fill_in_fadt(fadt);
 
 	header->checksum =
 	    acpi_checksum((void *) fadt, header->length);
diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.h
index 884fd6697b..47272b8c6e 100644
--- a/src/mainboard/intel/wtm2/gpio.h
+++ b/src/mainboard/intel/wtm2/gpio.h
@@ -20,105 +20,105 @@
 #ifndef INTEL_WTM2_GPIO_H
 #define INTEL_WTM2_GPIO_H
 
-#include "southbridge/intel/lynxpoint/lp_gpio.h"
+#include <broadwell/gpio.h>
 
-static const struct pch_lp_gpio_map mainboard_gpio_map[] = {
-	LP_GPIO_NATIVE,        /* 0: LPSS_UART1_RXD */
-	LP_GPIO_NATIVE,        /* 1: LPSS_UART1_TXD */
-	LP_GPIO_NATIVE,        /* 2: LPSS_UART1_RTS_N_R */
-	LP_GPIO_NATIVE,        /* 3: LPSS_UART1_CTS_N */
-	LP_GPIO_NATIVE,        /* 4: LPSS_I2C0_SDA_R */
-	LP_GPIO_NATIVE,        /* 5: LPSS_I2C0_SCL */
-	LP_GPIO_NATIVE,        /* 6: LPSS_I2C1_SDA */
-	LP_GPIO_NATIVE,        /* 7: LPSS_I2C1_SCL */
-	LP_GPIO_UNUSED,        /* 8: NGFF_SLTA_WIFI_WAKE_N */
-	LP_GPIO_UNUSED,        /* 9: ACCEL_INT2_MCP */
-	LP_GPIO_ACPI_SCI,      /* 10: SMC_RUNTIME_SCI_N */
-	LP_GPIO_UNUSED,        /* 11: AMB_THRM_R_N */
-	LP_GPIO_NATIVE,        /* 12: PM_LANPHY_ENABLE */
-	LP_GPIO_OUT_HIGH,      /* 13: USB32_P0_PWREN */
-	LP_GPIO_IRQ_EDGE,      /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */
-	LP_GPIO_OUT_HIGH,      /* 15: LAN_PWREN_N */
-	LP_GPIO_OUT_HIGH,      /* 16: LAN_RST_N */
-	LP_GPIO_OUT_LOW,       /* 17: CRIT_TEMP_REP_R_N */
-	LP_GPIO_UNUSED,        /* 18: TBT_FORCE_PWR */
-	LP_GPIO_INPUT,         /* 19: EC_IN_RW */
-	LP_GPIO_NATIVE,        /* 20: CK_REQ_P2_NGFFSLTA_N_R */
-	LP_GPIO_NATIVE,        /* 21: CK_PCIE_LAN_REQ_N */
-	LP_GPIO_NATIVE,        /* 22: CK_REQ_P4_TBT_N */
-	LP_GPIO_NATIVE,        /* 23: CK_REQ_P5_N */
-	LP_GPIO_OUT_LOW,       /* 24: ME_PG_LED */
-	LP_GPIO_INPUT,         /* 25: USB_WAKEOUT_N */
-	LP_GPIO_IRQ_EDGE,      /* 26: NFC_IRQ_MGP5 */
-	LP_GPIO_ACPI_SCI,      /* 27: SMC_WAKE_SCI_N */
-	LP_GPIO_OUT_LOW,       /* 28: PCH_NFC_RESET */
-	LP_GPIO_NATIVE,        /* 29: PCH_SLP_WLAN_N */
-	LP_GPIO_NATIVE,        /* 30: SUS_PWR_ACK_R */
-	LP_GPIO_NATIVE,        /* 31: AC_PRESENT_R */
-	LP_GPIO_NATIVE,        /* 32: PM_CKRUN_N */
-	LP_GPIO_OUT_LOW,       /* 33: SATA0_PHYSLP */
-	LP_GPIO_INPUT,         /* 34: ESATA_DET_N */
-	LP_GPIO_INPUT,         /* 35: SATA_DIRECT_PRSNT_R_N */
-	LP_GPIO_INPUT,         /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */
-	LP_GPIO_INPUT,         /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */
-	LP_GPIO_OUT_LOW,       /* 38: SATA1_PHYSLP_DIRECT */
-	LP_GPIO_ACPI_SMI,      /* 39: SMC_EXTSMI_N_R */
-	LP_GPIO_NATIVE,        /* 40: USB_OC_0_1_R_N */
-	LP_GPIO_NATIVE,        /* 41: USB_OC_2_6_R_N */
-	LP_GPIO_INPUT,         /* 42: TBT_CIO_PLUG_SMI_N_R */
-	LP_GPIO_OUT_HIGH,      /* 43: USB32_P1_PWREN */
-	LP_GPIO_INPUT,         /* 44: SENSOR_HUB_RST_N */
-	LP_GPIO_INPUT,         /* 45: GYRO_INT2_MCP_R */
-	LP_GPIO_OUT_HIGH,      /* 46: SNSR_HUB_PWREN */
-	LP_GPIO_IRQ_EDGE,      /* 47: SPI_TPM_HDR_IRQ_N */
-	LP_GPIO_OUT_HIGH,      /* 48: PCIE_TBT_RST_N */
-	LP_GPIO_INPUT,         /* 49: COMBO_JD */
-	LP_GPIO_IRQ_EDGE,      /* 50: TOUCH_PANEL_INTR_N */
-	LP_GPIO_OUT_HIGH,      /* 51: PCH_WIFI_RF_KILL_N */
-	LP_GPIO_OUT_HIGH,      /* 52: TOUCH_PNL_RST_N_R */
-	LP_GPIO_INPUT,         /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */
-	LP_GPIO_ACPI_SCI,      /* 54: NGFF_SLTB_SSD_MC_WAKE_N */
-	LP_GPIO_IRQ_EDGE,      /* 55: TOUCHPAD_INTR_N */
-	LP_GPIO_INPUT,         /* 56: NGFF_SLTB_WWAN_SSD_DET1 */
-	LP_GPIO_OUT_HIGH,      /* 57: NGFF_SLTB_WWAN_PWREN */
-	LP_GPIO_OUT_LOW,       /* 58: SLATEMODE_HALLOUT_R */
-	LP_GPIO_OUT_HIGH,      /* 59: USB2_CAM_PWREN */
-	LP_GPIO_OUT_LOW,       /* 60: USB_CR_PWREN_N */
-	LP_GPIO_NATIVE,        /* 61: PM_SUS_STAT_N */
-	LP_GPIO_NATIVE,        /* 62: SUS_CK */
-	LP_GPIO_NATIVE,        /* 63: SLP_S5_R_N */
-	LP_GPIO_NATIVE,        /* 64: LPSS_SDIO_CLK_CMNHDR_R */
-	LP_GPIO_NATIVE,        /* 65: LPSS_SDIO_CMD_CMNHDR_R */
-	LP_GPIO_NATIVE,        /* 66: LPSS_SDIO_D0_CMNHDR_R */
-	LP_GPIO_NATIVE,        /* 67: LPSS_SDIO_D1_CMNHDR_R */
-	LP_GPIO_NATIVE,        /* 68: LPSS_SDIO_D2_CMNHDR_R */
-	LP_GPIO_NATIVE,        /* 69: LPSS_SDIO_D3_CMNHDR_R1 */
-	LP_GPIO_NATIVE,        /* 70: NGFF_SLTA_WIFI_PWREN_N_R */
-	LP_GPIO_OUT_HIGH,      /* 71: MPHY_PWREN */
-	LP_GPIO_NATIVE,        /* 72: PM_BATLOW_R_N */
-	LP_GPIO_NATIVE,        /* 73: PCH_NOT_N */
-	LP_GPIO_NATIVE,        /* 74: SML1_DATA */
-	LP_GPIO_NATIVE,        /* 75: SML1_CK */
-	LP_GPIO_OUT_HIGH,      /* 76: PCH_AUDIO_PWR_R */
-	LP_GPIO_OUT_LOW,       /* 77: PC_SLTB_SSD_RST_N_R */
-	LP_GPIO_INPUT,         /* 78: PM_EXTTS0_EC_N */
-	LP_GPIO_IRQ_EDGE,      /* 79: SIO1007_IRQ_N */
-	LP_GPIO_INPUT,         /* 80: PM_EXTTS1_R_N */
-	LP_GPIO_NATIVE,        /* 81: PCH_HDA_SPKR */
-	LP_GPIO_NATIVE,        /* 82: H_RCIN_N */
-	LP_GPIO_NATIVE,        /* 83: LPSS_GSPI0_CS_R_N */
-	LP_GPIO_NATIVE,        /* 84: LPSS_GSPI0_CLK_R */
-	LP_GPIO_NATIVE,        /* 85: LPSS_GSPI0_MISO_R */
-	LP_GPIO_NATIVE,        /* 86: LPSS_GSPI0_MOSI_BBS0_R */
-	LP_GPIO_NATIVE,        /* 87: LPSS_GSPI1_CS_R_N */
-	LP_GPIO_NATIVE,        /* 88: LPSS_GSPI1_CLK_R */
-	LP_GPIO_NATIVE,        /* 89: LPSS_GSPI1_MISO_R */
-	LP_GPIO_OUT_LOW,       /* 90: NGFF_SLTA_WIFI_RST_N */
-	LP_GPIO_NATIVE,        /* 91: LPSS_UART0_RXD */
-	LP_GPIO_NATIVE,        /* 92: LPSS_UART0_TXD */
-	LP_GPIO_NATIVE,        /* 93: LPSS_UART0_RTS_N */
-	LP_GPIO_NATIVE,        /* 94: LPSS_UART0_CTS_N */
-	LP_GPIO_END
+static const struct gpio_config mainboard_gpio_config[] = {
+	PCH_GPIO_NATIVE,        /* 0: LPSS_UART1_RXD */
+	PCH_GPIO_NATIVE,        /* 1: LPSS_UART1_TXD */
+	PCH_GPIO_NATIVE,        /* 2: LPSS_UART1_RTS_N_R */
+	PCH_GPIO_NATIVE,        /* 3: LPSS_UART1_CTS_N */
+	PCH_GPIO_NATIVE,        /* 4: LPSS_I2C0_SDA_R */
+	PCH_GPIO_NATIVE,        /* 5: LPSS_I2C0_SCL */
+	PCH_GPIO_NATIVE,        /* 6: LPSS_I2C1_SDA */
+	PCH_GPIO_NATIVE,        /* 7: LPSS_I2C1_SCL */
+	PCH_GPIO_UNUSED,        /* 8: NGFF_SLTA_WIFI_WAKE_N */
+	PCH_GPIO_UNUSED,        /* 9: ACCEL_INT2_MCP */
+	PCH_GPIO_ACPI_SCI,      /* 10: SMC_RUNTIME_SCI_N */
+	PCH_GPIO_UNUSED,        /* 11: AMB_THRM_R_N */
+	PCH_GPIO_NATIVE,        /* 12: PM_LANPHY_ENABLE */
+	PCH_GPIO_OUT_HIGH,      /* 13: USB32_P0_PWREN */
+	PCH_GPIO_IRQ_EDGE,      /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */
+	PCH_GPIO_OUT_HIGH,      /* 15: LAN_PWREN_N */
+	PCH_GPIO_OUT_HIGH,      /* 16: LAN_RST_N */
+	PCH_GPIO_OUT_LOW,       /* 17: CRIT_TEMP_REP_R_N */
+	PCH_GPIO_UNUSED,        /* 18: TBT_FORCE_PWR */
+	PCH_GPIO_INPUT,         /* 19: EC_IN_RW */
+	PCH_GPIO_NATIVE,        /* 20: CK_REQ_P2_NGFFSLTA_N_R */
+	PCH_GPIO_NATIVE,        /* 21: CK_PCIE_LAN_REQ_N */
+	PCH_GPIO_NATIVE,        /* 22: CK_REQ_P4_TBT_N */
+	PCH_GPIO_NATIVE,        /* 23: CK_REQ_P5_N */
+	PCH_GPIO_OUT_LOW,       /* 24: ME_PG_LED */
+	PCH_GPIO_INPUT,         /* 25: USB_WAKEOUT_N */
+	PCH_GPIO_IRQ_EDGE,      /* 26: NFC_IRQ_MGP5 */
+	PCH_GPIO_ACPI_SCI,      /* 27: SMC_WAKE_SCI_N */
+	PCH_GPIO_OUT_LOW,       /* 28: PCH_NFC_RESET */
+	PCH_GPIO_NATIVE,        /* 29: PCH_SLP_WLAN_N */
+	PCH_GPIO_NATIVE,        /* 30: SUS_PWR_ACK_R */
+	PCH_GPIO_NATIVE,        /* 31: AC_PRESENT_R */
+	PCH_GPIO_NATIVE,        /* 32: PM_CKRUN_N */
+	PCH_GPIO_OUT_LOW,       /* 33: SATA0_PHYSLP */
+	PCH_GPIO_INPUT,         /* 34: ESATA_DET_N */
+	PCH_GPIO_INPUT,         /* 35: SATA_DIRECT_PRSNT_R_N */
+	PCH_GPIO_INPUT,         /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */
+	PCH_GPIO_INPUT,         /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */
+	PCH_GPIO_OUT_LOW,       /* 38: SATA1_PHYSLP_DIRECT */
+	PCH_GPIO_ACPI_SMI,      /* 39: SMC_EXTSMI_N_R */
+	PCH_GPIO_NATIVE,        /* 40: USB_OC_0_1_R_N */
+	PCH_GPIO_NATIVE,        /* 41: USB_OC_2_6_R_N */
+	PCH_GPIO_INPUT,         /* 42: TBT_CIO_PLUG_SMI_N_R */
+	PCH_GPIO_OUT_HIGH,      /* 43: USB32_P1_PWREN */
+	PCH_GPIO_INPUT,         /* 44: SENSOR_HUB_RST_N */
+	PCH_GPIO_INPUT,         /* 45: GYRO_INT2_MCP_R */
+	PCH_GPIO_OUT_HIGH,      /* 46: SNSR_HUB_PWREN */
+	PCH_GPIO_IRQ_EDGE,      /* 47: SPI_TPM_HDR_IRQ_N */
+	PCH_GPIO_OUT_HIGH,      /* 48: PCIE_TBT_RST_N */
+	PCH_GPIO_INPUT,         /* 49: COMBO_JD */
+	PCH_GPIO_IRQ_EDGE,      /* 50: TOUCH_PANEL_INTR_N */
+	PCH_GPIO_OUT_HIGH,      /* 51: PCH_WIFI_RF_KILL_N */
+	PCH_GPIO_OUT_HIGH,      /* 52: TOUCH_PNL_RST_N_R */
+	PCH_GPIO_INPUT,         /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */
+	PCH_GPIO_ACPI_SCI,      /* 54: NGFF_SLTB_SSD_MC_WAKE_N */
+	PCH_GPIO_IRQ_EDGE,      /* 55: TOUCHPAD_INTR_N */
+	PCH_GPIO_INPUT,         /* 56: NGFF_SLTB_WWAN_SSD_DET1 */
+	PCH_GPIO_OUT_HIGH,      /* 57: NGFF_SLTB_WWAN_PWREN */
+	PCH_GPIO_OUT_LOW,       /* 58: SLATEMODE_HALLOUT_R */
+	PCH_GPIO_OUT_HIGH,      /* 59: USB2_CAM_PWREN */
+	PCH_GPIO_OUT_LOW,       /* 60: USB_CR_PWREN_N */
+	PCH_GPIO_NATIVE,        /* 61: PM_SUS_STAT_N */
+	PCH_GPIO_NATIVE,        /* 62: SUS_CK */
+	PCH_GPIO_NATIVE,        /* 63: SLP_S5_R_N */
+	PCH_GPIO_NATIVE,        /* 64: LPSS_SDIO_CLK_CMNHDR_R */
+	PCH_GPIO_NATIVE,        /* 65: LPSS_SDIO_CMD_CMNHDR_R */
+	PCH_GPIO_NATIVE,        /* 66: LPSS_SDIO_D0_CMNHDR_R */
+	PCH_GPIO_NATIVE,        /* 67: LPSS_SDIO_D1_CMNHDR_R */
+	PCH_GPIO_NATIVE,        /* 68: LPSS_SDIO_D2_CMNHDR_R */
+	PCH_GPIO_NATIVE,        /* 69: LPSS_SDIO_D3_CMNHDR_R1 */
+	PCH_GPIO_NATIVE,        /* 70: NGFF_SLTA_WIFI_PWREN_N_R */
+	PCH_GPIO_OUT_HIGH,      /* 71: MPHY_PWREN */
+	PCH_GPIO_NATIVE,        /* 72: PM_BATLOW_R_N */
+	PCH_GPIO_NATIVE,        /* 73: PCH_NOT_N */
+	PCH_GPIO_NATIVE,        /* 74: SML1_DATA */
+	PCH_GPIO_NATIVE,        /* 75: SML1_CK */
+	PCH_GPIO_OUT_HIGH,      /* 76: PCH_AUDIO_PWR_R */
+	PCH_GPIO_OUT_LOW,       /* 77: PC_SLTB_SSD_RST_N_R */
+	PCH_GPIO_INPUT,         /* 78: PM_EXTTS0_EC_N */
+	PCH_GPIO_IRQ_EDGE,      /* 79: SIO1007_IRQ_N */
+	PCH_GPIO_INPUT,         /* 80: PM_EXTTS1_R_N */
+	PCH_GPIO_NATIVE,        /* 81: PCH_HDA_SPKR */
+	PCH_GPIO_NATIVE,        /* 82: H_RCIN_N */
+	PCH_GPIO_NATIVE,        /* 83: LPSS_GSPI0_CS_R_N */
+	PCH_GPIO_NATIVE,        /* 84: LPSS_GSPI0_CLK_R */
+	PCH_GPIO_NATIVE,        /* 85: LPSS_GSPI0_MISO_R */
+	PCH_GPIO_NATIVE,        /* 86: LPSS_GSPI0_MOSI_BBS0_R */
+	PCH_GPIO_NATIVE,        /* 87: LPSS_GSPI1_CS_R_N */
+	PCH_GPIO_NATIVE,        /* 88: LPSS_GSPI1_CLK_R */
+	PCH_GPIO_NATIVE,        /* 89: LPSS_GSPI1_MISO_R */
+	PCH_GPIO_OUT_LOW,       /* 90: NGFF_SLTA_WIFI_RST_N */
+	PCH_GPIO_NATIVE,        /* 91: LPSS_UART0_RXD */
+	PCH_GPIO_NATIVE,        /* 92: LPSS_UART0_TXD */
+	PCH_GPIO_NATIVE,        /* 93: LPSS_UART0_RTS_N */
+	PCH_GPIO_NATIVE,        /* 94: LPSS_UART0_CTS_N */
+	PCH_GPIO_END
 };
 
 #endif
diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c
index a6839fc343..92d03076c1 100644
--- a/src/mainboard/intel/wtm2/mainboard.c
+++ b/src/mainboard/intel/wtm2/mainboard.c
@@ -31,7 +31,6 @@
 #include <arch/io.h>
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
-#include <southbridge/intel/lynxpoint/pch.h>
 
 void mainboard_suspend_resume(void)
 {
@@ -39,8 +38,6 @@ void mainboard_suspend_resume(void)
 	outb(0xcb, 0xb2);
 }
 
-
-
 // mainboard_enable is executed as first thing after
 // enumerate_buses().
 
diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c
index bcc94d6f2b..bec0b615f1 100644
--- a/src/mainboard/intel/wtm2/mainboard_smi.c
+++ b/src/mainboard/intel/wtm2/mainboard_smi.c
@@ -20,11 +20,8 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/me.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <cpu/intel/haswell/haswell.h>
+#include <broadwell/nvs.h>
+#include <broadwell/smm.h>
 
 int mainboard_io_trap_handler(int smif)
 {
@@ -46,26 +43,3 @@ int mainboard_io_trap_handler(int smif)
 	//gnvs->smif = 0;
 	return 1;
 }
-
-#define APMC_FINALIZE 0xcb
-
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 apmc)
-{
-	switch (apmc) {
-	case APMC_FINALIZE:
-		if (mainboard_finalized) {
-			printk(BIOS_DEBUG, "SMI#: Already finalized\n");
-			return 0;
-		}
-
-		intel_pch_finalize_smm();
-		intel_northbridge_haswell_finalize_smm();
-		intel_cpu_haswell_finalize_smm();
-
-		mainboard_finalized = 1;
-		break;
-	}
-	return 0;
-}
diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c
new file mode 100644
index 0000000000..a33dddfe30
--- /dev/null
+++ b/src/mainboard/intel/wtm2/pei_data.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <broadwell/gpio.h>
+#include <broadwell/pei_data.h>
+#include <broadwell/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	/* One installed DIMM per channel */
+	pei_data->dimm_channel0_disabled = 2;
+	pei_data->dimm_channel1_disabled = 2;
+
+	pei_data->spd_addresses[0] = 0xa2;
+	pei_data->spd_addresses[2] = 0xa2;
+
+	pei_data_usb2_port(pei_data, 0, 0x40, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_FRONT_PANEL);
+	pei_data_usb2_port(pei_data, 1, 0x40, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_FRONT_PANEL);
+	pei_data_usb2_port(pei_data, 2, 0x40, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_FRONT_PANEL);
+	pei_data_usb2_port(pei_data, 3, 0x40, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_FRONT_PANEL);
+	pei_data_usb2_port(pei_data, 4, 0x40, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_FRONT_PANEL);
+	pei_data_usb2_port(pei_data, 5, 0x40, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_FRONT_PANEL);
+	pei_data_usb2_port(pei_data, 6, 0x40, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_FRONT_PANEL);
+	pei_data_usb2_port(pei_data, 7, 0x40, 0, USB_OC_PIN_SKIP,
+			   USB_PORT_FRONT_PANEL);
+
+	pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0);
+	pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0);
+	pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
+	pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c
index b831244bd5..41bef93345 100644
--- a/src/mainboard/intel/wtm2/romstage.c
+++ b/src/mainboard/intel/wtm2/romstage.c
@@ -18,123 +18,28 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <stdint.h>
-#include <stddef.h>
 #include <console/console.h>
-#include "cpu/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/raminit.h"
-#include "southbridge/intel/lynxpoint/pch.h"
-#include "southbridge/intel/lynxpoint/lp_gpio.h"
+#include <stdint.h>
+#include <string.h>
+#include <broadwell/gpio.h>
+#include <broadwell/pei_data.h>
+#include <broadwell/pei_wrapper.h>
+#include <broadwell/romstage.h>
 #include "gpio.h"
 
-const struct rcba_config_instruction rcba_config[] = {
-
-	/*
-	 *             GFX    INTA -> PIRQA (MSI)
-	 * D28IP_P1IP  WLAN   INTA -> PIRQB
-	 * D28IP_P4IP  ETH0   INTB -> PIRQC
-	 * D29IP_E1P   EHCI1  INTA -> PIRQD
-	 * D20IP_XHCI  XHCI   INTA -> PIRQA
-	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
-	 * D31IP_SMIP  SMBUS  INTB -> PIRQG
-	 * D31IP_TTIP  THRT   INTC -> PIRQH
-	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
-	 */
-
-	/* Device interrupt pin register (board specific) */
-	RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
-			(INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
-	RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
-	RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
-			(INTB << D28IP_P4IP)),
-	RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
-	RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
-	RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)),
-	RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
-	RCBA_SET_REG_32(D20IR, (INTA << D20IP_XHCI)),
-
-	/* Device interrupt route registers */
-	RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)),
-	RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)),
-	RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)),
-	RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)),
-	RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),
-	RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
-	RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
-	RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
-	RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
-	RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQA, 0, 0, 0)),
-
-	/* Disable unused devices (board specific) */
-	RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+	struct pei_data pei_data;
 
-	RCBA_END_CONFIG,
-};
+	post_code(0x32);
 
-void mainboard_romstage_entry(unsigned long bist)
-{
-	struct pei_data pei_data = {
-		.pei_version = PEI_VERSION,
-		.mchbar = DEFAULT_MCHBAR,
-		.dmibar = DEFAULT_DMIBAR,
-		.epbar = DEFAULT_EPBAR,
-		.pciexbar = DEFAULT_PCIEXBAR,
-		.smbusbar = SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_ADDR,
-		.rcba = DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.temp_mmio_base = 0xfed08000,
-		.system_type = 5, /* ULT */
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa2, 0x00, 0xa2, 0x00 },
-		.ec_present = 1,
-		// 0 = leave channel enabled
-		// 1 = disable dimm 0 on channel
-		// 2 = disable dimm 1 on channel
-		// 3 = disable dimm 0+1 on channel
-		.dimm_channel0_disabled = 2,
-		.dimm_channel1_disabled = 2,
-		.max_ddr3_freq = 1600,
-		.usb2_ports = {
-			/* Length, Enable, OCn# */
-			{ 0x40, 1, USB_OC_PIN_SKIP, /* P0: */
-			  USB_PORT_FRONT_PANEL },
-			{ 0x40, 1, USB_OC_PIN_SKIP, /* P1: */
-			  USB_PORT_FRONT_PANEL },
-			{ 0x40, 1, USB_OC_PIN_SKIP, /* P2: */
-			  USB_PORT_FRONT_PANEL },
-			{ 0x40, 1, USB_OC_PIN_SKIP, /* P3: */
-			  USB_PORT_FRONT_PANEL },
-			{ 0x40, 1, USB_OC_PIN_SKIP, /* P4: */
-			  USB_PORT_FRONT_PANEL },
-			{ 0x40, 1, USB_OC_PIN_SKIP, /* P5: */
-			  USB_PORT_FRONT_PANEL },
-			{ 0x40, 1, USB_OC_PIN_SKIP, /* P6: */
-			  USB_PORT_FRONT_PANEL },
-			{ 0x40, 0, USB_OC_PIN_SKIP, /* P7: */
-			  USB_PORT_FRONT_PANEL },
-		},
-		.usb3_ports = {
-			/* Enable, OCn# */
-			{ 1, USB_OC_PIN_SKIP }, /* P1; */
-			{ 1, USB_OC_PIN_SKIP }, /* P2; */
-			{ 1, USB_OC_PIN_SKIP }, /* P3; */
-			{ 1, USB_OC_PIN_SKIP }, /* P4; */
-		},
-	};
+	/* Initialize GPIOs */
+	init_gpios(mainboard_gpio_config);
 
-	struct romstage_params romstage_params = {
-		.pei_data = &pei_data,
-		.gpio_map = &mainboard_gpio_map,
-		.rcba_config = &rcba_config[0],
-		.bist = bist,
-		.copy_spd = NULL,
-	};
+	/* Fill out PEI DATA */
+	memset(&pei_data, 0, sizeof(pei_data));
+	mainboard_fill_pei_data(&pei_data);
+	rp->pei_data = &pei_data;
 
-	/* Call into the real romstage main with this board's attributes. */
-	romstage_common(&romstage_params);
+	romstage_common(rp);
 }