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author | Steven J. Magnani <steve@digidescorp.com> | 2005-09-14 13:49:04 +0000 |
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committer | Steven J. Magnani <steve@digidescorp.com> | 2005-09-14 13:49:04 +0000 |
commit | 0b1a5a4a920a59092b4c6d1d634e00786681a2b8 (patch) | |
tree | db55111fa035c065062b37fbeaa6d02cdb9feffb /src/mainboard/intel/xe7501devkit/bus.h | |
parent | ffc83041b7d2600210e581f6ad897e9c14a60afa (diff) | |
download | coreboot-0b1a5a4a920a59092b4c6d1d634e00786681a2b8.tar.xz |
Initial support for Intel XE7501DEVKIT.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel/xe7501devkit/bus.h')
-rw-r--r-- | src/mainboard/intel/xe7501devkit/bus.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/mainboard/intel/xe7501devkit/bus.h b/src/mainboard/intel/xe7501devkit/bus.h new file mode 100644 index 0000000000..0a99bb2808 --- /dev/null +++ b/src/mainboard/intel/xe7501devkit/bus.h @@ -0,0 +1,17 @@ +#ifndef XE7501DEVKIT_BUS_H_INCLUDED
+#define XE7501DEVKIT_BUS_H_INCLUDED
+
+// These were determined by seeing how LinuxBIOS enumerates the various
+// PCI (and PCI-like) buses on the board.
+
+#define PCI_BUS_CHIPSET 0
+#define PCI_BUS_E7501_HI_B 1 // P64H2#2
+#define PCI_BUS_P64H2_2_B 2 // P64H2#2 bus B
+#define PCI_BUS_P64H2_2_A 3 // P64H2#2 bus A
+#define PCI_BUS_E7501_HI_D 4 // P64H2#1
+#define PCI_BUS_P64H2_1_B 5 // P64H2#1 bus B
+#define PCI_BUS_P64H2_1_A 6 // P64H2#1 bus A
+#define PCI_BUS_ICH3 7 // ICH3-S
+#define SUPERIO_BUS 8 // (arbitrary but unique bus #)
+
+#endif // XE7501DEVKIT_BUS_H_INCLUDED
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