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| author | Steven J. Magnani <steve@digidescorp.com> | 2005-09-14 13:49:04 +0000 |
|---|---|---|
| committer | Steven J. Magnani <steve@digidescorp.com> | 2005-09-14 13:49:04 +0000 |
| commit | 0b1a5a4a920a59092b4c6d1d634e00786681a2b8 (patch) | |
| tree | db55111fa035c065062b37fbeaa6d02cdb9feffb /src/mainboard/intel/xe7501devkit/failover.c | |
| parent | ffc83041b7d2600210e581f6ad897e9c14a60afa (diff) | |
| download | coreboot-0b1a5a4a920a59092b4c6d1d634e00786681a2b8.tar.xz | |
Initial support for Intel XE7501DEVKIT.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel/xe7501devkit/failover.c')
| -rw-r--r-- | src/mainboard/intel/xe7501devkit/failover.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/mainboard/intel/xe7501devkit/failover.c b/src/mainboard/intel/xe7501devkit/failover.c new file mode 100644 index 0000000000..68a1fec4eb --- /dev/null +++ b/src/mainboard/intel/xe7501devkit/failover.c @@ -0,0 +1,47 @@ +#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "pc80/mc146818rtc_early.c"
+#include "southbridge/intel/i82801ca/cmos_failover.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/intel/e7501/reset_test.c"
+
+static unsigned long main(unsigned long bist)
+{
+ /* Is this a deliberate reset by the bios */
+ if (bios_reset_detected() && last_boot_normal()) {
+ goto normal_image;
+ }
+ /* This is the primary cpu how should I boot? */
+ else {
+
+ check_cmos_failed();
+
+ if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ }
+ normal_image:
+ asm volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
+#if 0
+ cpu_reset:
+ asm volatile ("jmp __cpu_reset"
+ : /* outputs */
+ : "a"(bist) /* inputs */
+ : /* clobbers */
+ );
+#endif
+ fallback_image:
+ return bist;
+}
|