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| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-05 13:05:54 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-04-21 14:21:56 +0000 |
| commit | 5d13e7fdcd11f2c78ae2518c33b404932e4650c3 (patch) | |
| tree | ea79307fa9b75b38b59ab88a5fdfaa36b06b38e0 /src/mainboard/intel | |
| parent | 0c0d49229db9ef68a5ea9267296e900ac7274da8 (diff) | |
| download | coreboot-5d13e7fdcd11f2c78ae2518c33b404932e4650c3.tar.xz | |
soc/intel/alderlake: Drop unused `PrmrrSize` from devicetree
The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the
devicetree option's value is not used anywhere, drop it.
Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_m.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb | 1 |
3 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 5ca8468118..4604c27928 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -52,8 +52,6 @@ chip soc/intel/alderlake register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" - register "PrmrrSize" = "0" - # Enable PCH PCIE RP 5 using CLK 2 register "pch_pcie_rp[PCH_RP(5)]" = "{ .clk_src = 2, diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index c6c2537978..a1edf6dd73 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -35,8 +35,6 @@ chip soc/intel/alderlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PrmrrSize" = "0" - #Enable PCH PCIE RP 4 using CLK 5 register "pch_pcie_rp[PCH_RP(4)]" = "{ .clk_src = 5, diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index ac7c31d3cf..9464f10fe0 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -47,7 +47,6 @@ chip soc/intel/alderlake register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PrmrrSize" = "0" # Enable PCH PCIE RP 5 using CLK 1 register "pch_pcie_rp[PCH_RP(5)]" = "{ |