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authorAlexandru Gagniuc <alexandrux.gagniuc@intel.com>2016-05-03 11:02:14 -0700
committerMartin Roth <martinroth@google.com>2016-05-06 18:56:44 +0200
commit5ff7031f729a319f35c9acdc1526a115a925398e (patch)
tree22eca843808ea0800ba6c4782ed4ed940a11a765 /src/mainboard/intel
parentbdd921c7720d372399ab57796eb9dcba48530249 (diff)
downloadcoreboot-5ff7031f729a319f35c9acdc1526a115a925398e.tar.xz
intel/amenia: Configure the bridge to ChromeEC in the bootblock
Communication with ChromeEC, which is on the LPC bus, is needed early on for vboot purposes. I'm not sure if Google wants to have the interface available in bootblock or romstage, so we're confguring it in the bootblock. The bridge is automatically reconfigured during ramstage in a way in which we don't get duplicate windows opened upt to LPC. Change-Id: I77887e881d23f655495dec2687394409a5bb8cf5 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14588 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/amenia/Makefile.inc2
-rw-r--r--src/mainboard/intel/amenia/bootblock.c31
2 files changed, 33 insertions, 0 deletions
diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc
index f05e03b1bd..8d4d5f7058 100644
--- a/src/mainboard/intel/amenia/Makefile.inc
+++ b/src/mainboard/intel/amenia/Makefile.inc
@@ -1,3 +1,5 @@
+bootblock-y += bootblock.c
+
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
diff --git a/src/mainboard/intel/amenia/bootblock.c b/src/mainboard/intel/amenia/bootblock.c
new file mode 100644
index 0000000000..c483d777c7
--- /dev/null
+++ b/src/mainboard/intel/amenia/bootblock.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/lpc.h>
+
+void bootblock_mainboard_init(void)
+{
+ /* Configure pads so that our signals make it out of the SOC. */
+ lpc_configure_pads();
+
+ /* Ports 62/66, 60/64, and 200->208 are needed by ChromeEC */
+ lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
+
+ /* Ports 800 -> 9ff are used by ChromeEC. */
+ lpc_open_pmio_window(0x800, 0x200);
+}