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| author | Anil Kumar <anil.kumar.k@intel.corp-partner.google.com> | 2021-04-22 11:35:36 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-05 20:27:13 +0000 |
| commit | 88dd4f705aac9f5b3bf21c8d7a4e516167ac32c5 (patch) | |
| tree | cdfa26d8aff6fd6427a52d27534808a543345231 /src/mainboard/intel | |
| parent | 54c3662a571a6c95bffbaf117a5c5c9255b18917 (diff) | |
| download | coreboot-88dd4f705aac9f5b3bf21c8d7a4e516167ac32c5.tar.xz | |
mb/intel/adlrvp: Enable support for Chrome OS mode switches
Branch=none
Test=build and boot ADL-M RVP. Test recovery mode using servo command
dut-control power_state:rec
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I771f0ef14b1c273f9d1af22c96de0eabd08e9a8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52614
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/Kconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 8a64e49735..ce5665c567 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -80,6 +80,7 @@ config ADL_CHROME_EC select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_BOARDID select EC_ACPI + select EC_GOOGLE_CHROMEEC_LPC config ADL_INTEL_EC bool "Intel EC" @@ -90,6 +91,7 @@ endchoice config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA + select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC config UART_FOR_CONSOLE int |