summaryrefslogtreecommitdiff
path: root/src/mainboard/intel
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2017-08-15 20:59:09 +0200
committerArthur Heymans <arthur@aheymans.xyz>2018-01-14 21:43:25 +0000
commitb451df2f400ba12fff440247330f8b57a93034bd (patch)
tree8bb52821a42aaaea2e614910d97b1ae4e690b7c2 /src/mainboard/intel
parente4a016ff17b455a8acd0ea72b30caabb622ce224 (diff)
downloadcoreboot-b451df2f400ba12fff440247330f8b57a93034bd.tar.xz
mb/*/*/romstage.c: Clean up targets with i82801gx
Things cleaned up in this patch: * Add macros for the GENx_DEC registers; * replace many magic numbers by macros; * remove many writes to DxxIP since they were 'setting' reset default values; * fix some comments about decode ranges. Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/d510mo/romstage.c44
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c36
2 files changed, 33 insertions, 47 deletions
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index c6406e6f9f..b2044c1a30 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -57,15 +57,15 @@ static void mb_gpio_init(void)
static void nm10_enable_lpc(void)
{
/* Disable Serial IRQ */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);
/* Decode range */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80,
- pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x80) | 0x0010);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
- CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC,
+ pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
+ | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN
+ | COMB_LPC_EN);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291);
}
static void rcba_config(void)
@@ -74,29 +74,19 @@ static void rcba_config(void)
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- RCBA32(0x3108) = 0x10004321;
-
- RCBA32(0x3104) = 0x00002100;
-
- /* PCIe Interrupts */
- RCBA32(0x310c) = 0x00214321;
- /* HD Audio Interrupt */
- RCBA32(0x3110) = 0x00000001;
-
/* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x0146;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x0146;
+ RCBA16(D31IR) = 0x0132;
+ RCBA16(D30IR) = 0x0146;
+ RCBA16(D29IR) = 0x0237;
+ RCBA16(D28IR) = 0x3201;
+ RCBA16(D27IR) = 0x0146;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
- RCBA32(0x3418) = 0x003000e2;
- RCBA32(0x3418) |= 1;
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD
+ | FD_PATA;
+ RCBA32(FD) |= 1;
}
void mainboard_romstage_entry(unsigned long bist)
@@ -113,7 +103,7 @@ void mainboard_romstage_entry(unsigned long bist)
enable_lapic();
/* Disable watchdog timer */
- RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
+ RCBA32(GCS) = RCBA32(GCS) | 0x20;
/* Set southbridge and Super I/O GPIOs. */
mb_gpio_init();
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index e769fc522b..27c1e3e7db 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -40,13 +40,14 @@
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
// Set COM1/COM2 decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
// Enable COM1
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
+ | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
// Enable SuperIO Power Management Events
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c0681);
}
static void rcba_config(void)
@@ -55,26 +56,21 @@ static void rcba_config(void)
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
-
/* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x0146;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x0146;
+ RCBA16(D31IR) = 0x0132;
+ RCBA16(D30IR) = 0x0146;
+ RCBA16(D29IR) = 0x0237;
+ RCBA16(D28IR) = 0x3201;
+ RCBA16(D27IR) = 0x0146;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Disable unused devices */
- //RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
- // RCBA32(0x3418) |= (1 << 0); // Required.
- // FIXME look me up!
- RCBA32(0x3418) = 0x003204e1;
+ // FIXME devicetree disables pcie3 not 2.
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE2 | (1 << 10) | FD_INTLAN
+ | FD_ACMOD | FD_ACAUD;
+ RCBA32(FD) |= 1;
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
@@ -119,7 +115,7 @@ static void early_ich7_init(void)
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);