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authorPatrick Georgi <pgeorgi@google.com>2014-11-28 22:35:36 +0100
committerPatrick Georgi <pgeorgi@google.com>2014-11-30 12:20:07 +0100
commitbd79c5eaf1f13f33c43c99657f24fa4c0330619a (patch)
treec20d6e5e00fcf3494d1c3fdd2d84b97ae34a21ea /src/mainboard/intel
parent1b2f2a071488bd15ce80194e85d318cd44659e54 (diff)
downloadcoreboot-bd79c5eaf1f13f33c43c99657f24fa4c0330619a.tar.xz
Replace hlt() loops with halt()
Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/cougar_canyon2/romstage.c5
-rw-r--r--src/mainboard/intel/emeraldlake2/romstage.c5
2 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 9ac70ef78d..c90ece2e56 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -31,6 +31,7 @@
#include <pc80/mc146818rtc.h>
#include <cbmem.h>
#include <console/console.h>
+#include <halt.h>
#include <reset.h>
#include "superio/smsc/sio1007/chip.h"
#include <fsp_util.h>
@@ -49,9 +50,7 @@
static inline void reset_system(void)
{
hard_reset();
- while (1) {
- hlt();
- }
+ halt();
}
static void pch_enable_lpc(void)
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index d50093e08d..76edf7fd0d 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -38,6 +38,7 @@
#include <arch/cpu.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
+#include <halt.h>
#include "gpio.h"
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
@@ -203,7 +204,7 @@ void main(unsigned long bist)
/* System is not happy after keyboard reset... */
printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
outb(0x6, 0xcf9);
- hlt();
+ halt();
}
/* Perform some early chipset initialization required
@@ -249,7 +250,7 @@ void main(unsigned long bist)
if (boot_mode==2 && !cbmem_was_initted) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
- hlt();
+ halt();
}
northbridge_romstage_finalize(boot_mode==2);