Remove the wtm1 mainboard

This was an early bring-up reference board for ULT but it is no
longer being worked on and was never complete enough to be useful
and I no longer have a board so it is already stale and untested.

All ULT bring-up work has moved to the wtm2 mainboard instead.

Change-Id: If64d61bf7a3fc8c9e16096ffc28fa4128aa99477
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3231
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

23 files changed, 0 insertions, 2354 deletions

diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig
index 3594a30c5a..bb15bc17fb 100644
--- a/src/mainboard/intel/Kconfig
+++ b/src/mainboard/intel/Kconfig
@@ -21,8 +21,6 @@ config BOARD_INTEL_XE7501DEVKIT
 	bool "XE7501devkit"
 config BOARD_INTEL_BASKING_RIDGE
 	bool "Basking Ridge CRB"
-config BOARD_INTEL_WTM1
-	bool "Whitetip Mountain 1 CRB"
 config BOARD_INTEL_WTM2
 	bool "Whitetip Mountain 2 CRB"
 
@@ -37,7 +35,6 @@ source "src/mainboard/intel/jarrell/Kconfig"
 source "src/mainboard/intel/mtarvon/Kconfig"
 source "src/mainboard/intel/truxton/Kconfig"
 source "src/mainboard/intel/xe7501devkit/Kconfig"
-source "src/mainboard/intel/wtm1/Kconfig"
 source "src/mainboard/intel/wtm2/Kconfig"
 
 config MAINBOARD_VENDOR
diff --git a/src/mainboard/intel/wtm1/Kconfig b/src/mainboard/intel/wtm1/Kconfig
deleted file mode 100644
index 65db03f29a..0000000000
--- a/src/mainboard/intel/wtm1/Kconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-if BOARD_INTEL_WTM1
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select ARCH_X86
-	select CPU_INTEL_SOCKET_RPGA989
-	select NORTHBRIDGE_INTEL_HASWELL
-	select SOUTHBRIDGE_INTEL_LYNXPOINT
-	select INTEL_LYNXPOINT_LP
-	select BOARD_ROMSIZE_KB_8192
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-	select HAVE_ACPI_RESUME
-	select MMCONF_SUPPORT
-	select HAVE_SMI_HANDLER
-	select CHROMEOS
-	select EXTERNAL_MRC_BLOB
-
-config MAINBOARD_DIR
-	string
-	default intel/wtm1
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "WHITETIP MOUNTAIN 1"
-
-config MMCONF_BASE_ADDRESS
-	hex
-	default 0xf0000000
-
-config IRQ_SLOT_COUNT
-	int
-	default 18
-
-config MAX_CPUS
-	int
-	default 16
-
-config VGA_BIOS_FILE
-	string
-	default "pci8086,0166.rom"
-
-endif # BOARD_INTEL_WTM1
diff --git a/src/mainboard/intel/wtm1/Makefile.inc b/src/mainboard/intel/wtm1/Makefile.inc
deleted file mode 100644
index 658c96c77e..0000000000
--- a/src/mainboard/intel/wtm1/Makefile.inc
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2011 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
diff --git a/src/mainboard/intel/wtm1/acpi/chromeos.asl b/src/mainboard/intel/wtm1/acpi/chromeos.asl
deleted file mode 100644
index c6b258b4e2..0000000000
--- a/src/mainboard/intel/wtm1/acpi/chromeos.asl
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-Name(OIPG, Package() {
-	// This GPIO is not available but the package cannot be empty
-	Package () { 0x0001, 0, 0, "LynxPoint" }, // recovery
-})
diff --git a/src/mainboard/intel/wtm1/acpi/ec.asl b/src/mainboard/intel/wtm1/acpi/ec.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/wtm1/acpi/ec.asl
+++ /dev/null
diff --git a/src/mainboard/intel/wtm1/acpi/haswell_pci_irqs.asl b/src/mainboard/intel/wtm1/acpi/haswell_pci_irqs.asl
deleted file mode 100644
index a8b6b5f739..0000000000
--- a/src/mainboard/intel/wtm1/acpi/haswell_pci_irqs.asl
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for IvyBridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, 0, 16 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, 0, 22 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, 0, 17 },
-			Package() { 0x001cffff, 1, 0, 18 },
-			Package() { 0x001cffff, 2, 0, 19 },
-			Package() { 0x001cffff, 3, 0, 20 },
-			// EHCI	  			0:1d.0
-			Package() { 0x001dffff, 0, 0, 19 },
-			// XHCI	  			0:14.0
-			Package() { 0x0014ffff, 0, 0, 16 },
-			// LPC devices			0:1f.0
-			Package() { 0x001fffff, 0, 0, 21 },
-			Package() { 0x001fffff, 1, 0, 22 },
-			Package() { 0x001fffff, 2, 0, 23 },
-			Package() { 0x001fffff, 3, 0, 16 },
-			// Serial IO                    0:15.0
-			Package() { 0x0015ffff, 0, 0, 16 },
-			Package() { 0x0015ffff, 1, 0, 17 },
-			Package() { 0x0015ffff, 2, 0, 18 },
-			Package() { 0x0015ffff, 3, 0, 19 },
-			// SDIO                         0:17.0
-			Package() { 0x0017ffff, 0, 0, 16 },
-		})
-	} Else {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
-			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
-			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
-			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
-		})
-	}
-}
-
diff --git a/src/mainboard/intel/wtm1/acpi/mainboard.asl b/src/mainboard/intel/wtm1/acpi/mainboard.asl
deleted file mode 100644
index 6b15331b81..0000000000
--- a/src/mainboard/intel/wtm1/acpi/mainboard.asl
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-Device (PWRB)
-{
-	Name(_HID, EisaId("PNP0C0C"))
-
-	// Wake
-	Name(_PRW, Package(){0x1d, 0x05})
-}
diff --git a/src/mainboard/intel/wtm1/acpi/platform.asl b/src/mainboard/intel/wtm1/acpi/platform.asl
deleted file mode 100644
index e0693928fa..0000000000
--- a/src/mainboard/intel/wtm1/acpi/platform.asl
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
-	APMC, 8,	// APM command
-	APMS, 8		// APM status
-}
-
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
-	DBG0, 8
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
-	Store (Arg0, SMIF)	// SMI Function
-	Store (0, TRP0)		// Generate trap
-	Return (SMIF)		// Return value of SMI handler
-}
-
-/* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
-Method(_PIC, 1)
-{
-	// Remember the OS' IRQ routing choice.
-	Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
-	Return(Package(){0,0})
-}
-
diff --git a/src/mainboard/intel/wtm1/acpi/superio.asl b/src/mainboard/intel/wtm1/acpi/superio.asl
deleted file mode 100644
index 9092a6c79d..0000000000
--- a/src/mainboard/intel/wtm1/acpi/superio.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Values should match those defined in devicetree.cb */
diff --git a/src/mainboard/intel/wtm1/acpi/thermal.asl b/src/mainboard/intel/wtm1/acpi/thermal.asl
deleted file mode 100644
index 00a8750a36..0000000000
--- a/src/mainboard/intel/wtm1/acpi/thermal.asl
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-// Thermal Zone
-
-Scope (\_TZ)
-{
-	ThermalZone (THRM)
-	{
-		Name (_TC1, 0x02)
-		Name (_TC2, 0x05)
-
-		// Thermal zone polling frequency: 0 seconds
-		Name (_TZP, 0)
-
-		// Thermal sampling period for passive cooling: 2 seconds
-		Name (_TSP, 20)
-
-		// Convert from Degrees C to 1/10 Kelvin for ACPI
-		Method (CTOK, 1) {
-			// 10th of Degrees C
-			Multiply (Arg0, 10, Local0)
-
-			// Convert to Kelvin
-			Add (Local0, 2732, Local0)
-
-			Return (Local0)
-		}
-
-		// Threshold for OS to shutdown
-		Method (_CRT, 0, Serialized)
-		{
-			Return (CTOK (\TCRT))
-		}
-
-		// Threshold for passive cooling
-		Method (_PSV, 0, Serialized)
-		{
-			Return (CTOK (\TPSV))
-		}
-
-		// Processors used for passive cooling
-		Method (_PSL, 0, Serialized)
-		{
-			Return (\PPKG ())
-		}
-
-		Method (_TMP, 0, Serialized)
-		{
-			Return (CTOK (30))
-		}
-
-		Method (_AC0) {
-			If (LLessEqual (\FLVL, 0)) {
-				Return (CTOK (\F0OF))
-			} Else {
-				Return (CTOK (\F0ON))
-			}
-		}
-
-		Method (_AC1) {
-			If (LLessEqual (\FLVL, 1)) {
-				Return (CTOK (\F1OF))
-			} Else {
-				Return (CTOK (\F1ON))
-			}
-		}
-
-		Method (_AC2) {
-			If (LLessEqual (\FLVL, 2)) {
-				Return (CTOK (\F2OF))
-			} Else {
-				Return (CTOK (\F2ON))
-			}
-		}
-
-		Method (_AC3) {
-			If (LLessEqual (\FLVL, 3)) {
-				Return (CTOK (\F3OF))
-			} Else {
-				Return (CTOK (\F3ON))
-			}
-		}
-
-		Method (_AC4) {
-			If (LLessEqual (\FLVL, 4)) {
-				Return (CTOK (\F4OF))
-			} Else {
-				Return (CTOK (\F4ON))
-			}
-		}
-
-		Name (_AL0, Package () { FAN0 })
-		Name (_AL1, Package () { FAN1 })
-		Name (_AL2, Package () { FAN2 })
-		Name (_AL3, Package () { FAN3 })
-		Name (_AL4, Package () { FAN4 })
-
-		PowerResource (FNP0, 0, 0)
-		{
-			Method (_STA) {
-				If (LLessEqual (\FLVL, 0)) {
-					Return (One)
-				} Else {
-					Return (Zero)
-				}
-			}
-			Method (_ON)  {
-				Store (0, \FLVL)
-				Notify (\_TZ.THRM, 0x81)
-			}
-			Method (_OFF) {
-				Store (1, \FLVL)
-				Notify (\_TZ.THRM, 0x81)
-			}
-		}
-
-		PowerResource (FNP1, 0, 0)
-		{
-			Method (_STA) {
-				If (LLessEqual (\FLVL, 1)) {
-					Return (One)
-				} Else {
-					Return (Zero)
-				}
-			}
-			Method (_ON)  {
-				Store (1, \FLVL)
-				Notify (\_TZ.THRM, 0x81)
-			}
-			Method (_OFF) {
-				Store (2, \FLVL)
-				Notify (\_TZ.THRM, 0x81)
-			}
-		}
-
-		PowerResource (FNP2, 0, 0)
-		{
-			Method (_STA) {
-				If (LLessEqual (\FLVL, 2)) {
-					Return (One)
-				} Else {
-					Return (Zero)
-				}
-			}
-			Method (_ON)  {
-				Store (2, \FLVL)
-				Notify (\_TZ.THRM, 0x81)
-			}
-			Method (_OFF) {
-				Store (3, \FLVL)
-				Notify (\_TZ.THRM, 0x81)
-			}
-		}
-
-		PowerResource (FNP3, 0, 0)
-		{
-			Method (_STA) {
-				If (LLessEqual (\FLVL, 3)) {
-					Return (One)
-				} Else {
-					Return (Zero)
-				}
-			}
-			Method (_ON)  {
-				Store (3, \FLVL)
-				Notify (\_TZ.THRM, 0x81)
-			}
-			Method (_OFF) {
-				Store (4, \FLVL)
-				Notify (\_TZ.THRM, 0x81)
-			}
-		}
-
-		PowerResource (FNP4, 0, 0)
-		{
-			Method (_STA) {
-				If (LLessEqual (\FLVL, 4)) {
-					Return (One)
-				} Else {
-					Return (Zero)
-				}
-			}
-			Method (_ON)  {
-				Store (4, \FLVL)
-				Notify (\_TZ.THRM, 0x81)
-			}
-			Method (_OFF) {
-				Store (4, \FLVL)
-				Notify (\_TZ.THRM, 0x81)
-			}
-		}
-
-		Device (FAN0)
-		{
-			Name (_HID, EISAID ("PNP0C0B"))
-			Name (_UID, 0)
-			Name (_PR0, Package () { FNP0 })
-		}
-
-		Device (FAN1)
-		{
-			Name (_HID, EISAID ("PNP0C0B"))
-			Name (_UID, 1)
-			Name (_PR0, Package () { FNP1 })
-		}
-
-		Device (FAN2)
-		{
-			Name (_HID, EISAID ("PNP0C0B"))
-			Name (_UID, 2)
-			Name (_PR0, Package () { FNP2 })
-		}
-
-		Device (FAN3)
-		{
-			Name (_HID, EISAID ("PNP0C0B"))
-			Name (_UID, 3)
-			Name (_PR0, Package () { FNP3 })
-		}
-
-		Device (FAN4)
-		{
-			Name (_HID, EISAID ("PNP0C0B"))
-			Name (_UID, 4)
-			Name (_PR0, Package () { FNP4 })
-		}
-	}
-}
-
diff --git a/src/mainboard/intel/wtm1/acpi/video.asl b/src/mainboard/intel/wtm1/acpi/video.asl
deleted file mode 100644
index 3ececa912b..0000000000
--- a/src/mainboard/intel/wtm1/acpi/video.asl
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-// Brightness write
-Method (BRTW, 1, Serialized)
-{
-	// TODO
-}
-
-// Hot Key Display Switch
-Method (HKDS, 1, Serialized)
-{
-	// TODO
-}
-
-// Lid Switch Display Switch
-Method (LSDS, 1, Serialized)
-{
-	// TODO
-}
-
-// Brightness Notification
-Method(BRTN,1,Serialized)
-{
-	// TODO (no displays defined yet)
-}
-
diff --git a/src/mainboard/intel/wtm1/acpi_tables.c b/src/mainboard/intel/wtm1/acpi_tables.c
deleted file mode 100644
index 16a1c6a9ed..0000000000
--- a/src/mainboard/intel/wtm1/acpi_tables.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <string.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/msr.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-
-extern const unsigned char AmlCode[];
-#if CONFIG_HAVE_ACPI_SLIC
-unsigned long acpi_create_slic(unsigned long current);
-#endif
-
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
-#include "thermal.h"
-
-static void acpi_update_thermal_table(global_nvs_t *gnvs)
-{
-	gnvs->f4of = FAN4_THRESHOLD_OFF;
-	gnvs->f4on = FAN4_THRESHOLD_ON;
-	gnvs->f4pw = FAN4_PWM;
-
-	gnvs->f3of = FAN3_THRESHOLD_OFF;
-	gnvs->f3on = FAN3_THRESHOLD_ON;
-	gnvs->f3pw = FAN3_PWM;
-
-	gnvs->f2of = FAN2_THRESHOLD_OFF;
-	gnvs->f2on = FAN2_THRESHOLD_ON;
-	gnvs->f2pw = FAN2_PWM;
-
-	gnvs->f1of = FAN1_THRESHOLD_OFF;
-	gnvs->f1on = FAN1_THRESHOLD_ON;
-	gnvs->f1pw = FAN1_PWM;
-
-	gnvs->f0of = FAN0_THRESHOLD_OFF;
-	gnvs->f0on = FAN0_THRESHOLD_ON;
-	gnvs->f0pw = FAN0_PWM;
-
-	gnvs->tcrt = CRITICAL_TEMPERATURE;
-	gnvs->tpsv = PASSIVE_TEMPERATURE;
-	gnvs->tmax = MAX_TEMPERATURE;
-}
-
-static void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	gnvs->apic = 1;
-	gnvs->mpen = 1; /* Enable Multi Processing */
-	gnvs->pcnt = dev_count_cpu();
-
-	/* Enable USB ports in S3 */
-	gnvs->s3u0 = 1;
-	gnvs->s3u1 = 1;
-
-	/* Disable USB ports in S5 */
-	gnvs->s5u0 = 0;
-	gnvs->s5u1 = 0;
-
-	/* CBMEM TOC */
-	gnvs->cmem = 0;
-
-	/* TPM Present */
-	gnvs->tpmp = 1;
-
-	/* IGD Displays */
-	gnvs->ndid = 3;
-	gnvs->did[0] = 0x80000100;
-	gnvs->did[1] = 0x80000240;
-	gnvs->did[2] = 0x80000410;
-	gnvs->did[3] = 0x80000410;
-	gnvs->did[4] = 0x00000005;
-
-#if CONFIG_CHROMEOS
-	// TODO(reinauer) this could move elsewhere?
-	chromeos_init_vboot(&(gnvs->chromeos));
-	/* Emerald Lake has no EC (?) */
-	gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
-#endif
-
-	acpi_update_thermal_table(gnvs);
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
-
-unsigned long acpi_fill_ssdt_generator(unsigned long current,
-					const char *oem_table_id)
-{
-	generate_cpu_entries();
-	return (unsigned long) (acpigen_get_current());
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
-	// Not implemented
-	return current;
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
-	/* No NUMA, no SRAT */
-	return current;
-}
-
-#define ALIGN_CURRENT current = (ALIGN(current, 16))
-unsigned long write_acpi_tables(unsigned long start)
-{
-	unsigned long current;
-	int i;
-	acpi_rsdp_t *rsdp;
-	acpi_rsdt_t *rsdt;
-	acpi_xsdt_t *xsdt;
-	acpi_hpet_t *hpet;
-	acpi_madt_t *madt;
-	acpi_mcfg_t *mcfg;
-	acpi_fadt_t *fadt;
-	acpi_facs_t *facs;
-#if CONFIG_HAVE_ACPI_SLIC
-	acpi_header_t *slic;
-#endif
-	acpi_header_t *ssdt;
-	acpi_header_t *dsdt;
-	global_nvs_t *gnvs;
-
-	current = start;
-
-	/* Align ACPI tables to 16byte */
-	ALIGN_CURRENT;
-
-	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
-
-	/* We need at least an RSDP and an RSDT Table */
-	rsdp = (acpi_rsdp_t *) current;
-	current += sizeof(acpi_rsdp_t);
-	ALIGN_CURRENT;
-	rsdt = (acpi_rsdt_t *) current;
-	current += sizeof(acpi_rsdt_t);
-	ALIGN_CURRENT;
-	xsdt = (acpi_xsdt_t *) current;
-	current += sizeof(acpi_xsdt_t);
-	ALIGN_CURRENT;
-
-	/* clear all table memory */
-	memset((void *) start, 0, current - start);
-
-	acpi_write_rsdp(rsdp, rsdt, xsdt);
-	acpi_write_rsdt(rsdt);
-	acpi_write_xsdt(xsdt);
-
-	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
-	facs = (acpi_facs_t *) current;
-	current += sizeof(acpi_facs_t);
-	ALIGN_CURRENT;
-	acpi_create_facs(facs);
-
-	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
-	dsdt = (acpi_header_t *) current;
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	current += dsdt->length;
-	memcpy(dsdt, &AmlCode, dsdt->length);
-
-	ALIGN_CURRENT;
-
-	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
-	fadt = (acpi_fadt_t *) current;
-	current += sizeof(acpi_fadt_t);
-	ALIGN_CURRENT;
-
-	acpi_create_fadt(fadt, facs, dsdt);
-	acpi_add_table(rsdp, fadt);
-
-	/*
-	 * We explicitly add these tables later on:
-	 */
-	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
-
-	hpet = (acpi_hpet_t *) current;
-	current += sizeof(acpi_hpet_t);
-	ALIGN_CURRENT;
-	acpi_create_intel_hpet(hpet);
-	acpi_add_table(rsdp, hpet);
-
-	/* If we want to use HPET Timers Linux wants an MADT */
-	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
-
-	madt = (acpi_madt_t *) current;
-	acpi_create_madt(madt);
-	current += madt->header.length;
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, madt);
-
-	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
-	mcfg = (acpi_mcfg_t *) current;
-	acpi_create_mcfg(mcfg);
-	current += mcfg->header.length;
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, mcfg);
-
-	/* Update GNVS pointer into CBMEM */
-	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-	if (!gnvs) {
-		printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n");
-		gnvs = (global_nvs_t *)current;
-	}
-
-	for (i=0; i < dsdt->length; i++) {
-		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
-			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
-			       "DSDT at offset 0x%04x -> %p\n", i, gnvs);
-			*(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs;
-			acpi_save_gnvs((unsigned long)gnvs);
-			break;
-		}
-	}
-
-	/* And fill it */
-	acpi_create_gnvs(gnvs);
-
-	/* And tell SMI about it */
-	smm_setup_structures(gnvs, NULL, NULL);
-
-	current += sizeof(global_nvs_t);
-	ALIGN_CURRENT;
-
-	/* We patched up the DSDT, so we need to recalculate the checksum */
-	dsdt->checksum = 0;
-	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
-
-	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
-		     dsdt->length);
-
-#if CONFIG_HAVE_ACPI_SLIC
-	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
-	slic = (acpi_header_t *)current;
-	current += acpi_create_slic(current);
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, slic);
-#endif
-
-	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
-	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
-	current += ssdt->length;
-	acpi_add_table(rsdp, ssdt);
-	ALIGN_CURRENT;
-
-	printk(BIOS_DEBUG, "current = %lx\n", current);
-	printk(BIOS_INFO, "ACPI: done.\n");
-	return current;
-}
diff --git a/src/mainboard/intel/wtm1/chromeos.c b/src/mainboard/intel/wtm1/chromeos.c
deleted file mode 100644
index f8960764f0..0000000000
--- a/src/mainboard/intel/wtm1/chromeos.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-
-#ifndef __PRE_RAM__
-#include <boot/coreboot_tables.h>
-
-#define GPIO_COUNT	6
-#define ACTIVE_LOW	0
-#define ACTIVE_HIGH	1
-
-static void fill_lb_gpio(struct lb_gpio *gpio, int num,
-			 int polarity, const char *name, int force)
-{
-	memset(gpio, 0, sizeof(*gpio));
-	gpio->port = num;
-	gpio->polarity = polarity;
-	if (force >= 0)
-		gpio->value = force;
-	else if (num >= 0)
-		gpio->value = get_gpio(num);
-	strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	struct lb_gpio *gpio;
-
-	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
-	gpios->count = GPIO_COUNT;
-
-	gpio = gpios->gpios;
-	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", 0);
-	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", 0); // force off
-	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", 1); // force on
-	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); // force open
-	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
-	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded);
-}
-#endif
-
-int get_developer_mode_switch(void)
-{
-	return 1; // force on
-}
-
-int get_recovery_mode_switch(void)
-{
-	return 0; // force off
-}
-
-int get_write_protect_state(void)
-{
-	return 0;
-}
-
diff --git a/src/mainboard/intel/wtm1/cmos.layout b/src/mainboard/intel/wtm1/cmos.layout
deleted file mode 100644
index afdd3c66ca..0000000000
--- a/src/mainboard/intel/wtm1/cmos.layout
+++ /dev/null
@@ -1,139 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-# -----------------------------------------------------------------
-entries
-
-#start-bit length  config config-ID    name
-#0            8       r       0        seconds
-#8            8       r       0        alarm_seconds
-#16           8       r       0        minutes
-#24           8       r       0        alarm_minutes
-#32           8       r       0        hours
-#40           8       r       0        alarm_hours
-#48           8       r       0        day_of_week
-#56           8       r       0        day_of_month
-#64           8       r       0        month
-#72           8       r       0        year
-# -----------------------------------------------------------------
-# Status Register A
-#80           4       r       0        rate_select
-#84           3       r       0        REF_Clock
-#87           1       r       0        UIP
-# -----------------------------------------------------------------
-# Status Register B
-#88           1       r       0        auto_switch_DST
-#89           1       r       0        24_hour_mode
-#90           1       r       0        binary_values_enable
-#91           1       r       0        square-wave_out_enable
-#92           1       r       0        update_finished_enable
-#93           1       r       0        alarm_interrupt_enable
-#94           1       r       0        periodic_interrupt_enable
-#95           1       r       0        disable_clock_updates
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-385          1       e       4        last_boot
-388          4       r       0        reboot_bits
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-392          3       e       5        baud_rate
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-400          1       e       2        hyper_threading
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-409          2       e       7        power_on_after_fail
-#411          5       r       0        unused
-
-# coreboot config options: bootloader
-#Used by ChromeOS:
-416        128       r        0        vbnv
-#544        440       r       0        unused
-
-# SandyBridge MRC Scrambler Seed values
-896         32        r       0        mrc_scrambler_seed
-928         32        r       0        mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-#1000        24       r       0        amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-5     0     115200
-5     1     57600
-5     2     38400
-5     3     19200
-5     4     9600
-5     5     4800
-5     6     2400
-5     7     1200
-6     1     Emergency
-6     2     Alert
-6     3     Critical
-6     4     Error
-6     5     Warning
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
-
-
diff --git a/src/mainboard/intel/wtm1/devicetree.cb b/src/mainboard/intel/wtm1/devicetree.cb
deleted file mode 100644
index be4fe51b41..0000000000
--- a/src/mainboard/intel/wtm1/devicetree.cb
+++ /dev/null
@@ -1,84 +0,0 @@
-chip northbridge/intel/haswell
-
-	# Enable DisplayPort 1 Hotplug with 6ms pulse
-	register "gpu_dp_d_hotplug" = "0x06"
-
-	# Enable DisplayPort 0 Hotplug with 6ms pulse
-	register "gpu_dp_c_hotplug" = "0x06"
-
-	# Enable DVI Hotplug with 6ms pulse
-	register "gpu_dp_b_hotplug" = "0x06"
-
-	device cpu_cluster 0 on
-		chip cpu/intel/socket_rPGA989
-			device lapic 0 on end
-		end
-		chip cpu/intel/haswell
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-
-			register "c1_battery" = "3"	# ACPI(C1) = MWAIT(C3)
-			register "c2_battery" = "4"	# ACPI(C2) = MWAIT(C6)
-			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)
-
-			register "c1_acpower" = "3"	# ACPI(C1) = MWAIT(C3)
-			register "c2_acpower" = "4"	# ACPI(C2) = MWAIT(C6)
-			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)
-		end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-
-		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
-			register "pirqa_routing" = "0x8b"
-			register "pirqb_routing" = "0x8a"
-			register "pirqc_routing" = "0x8b"
-			register "pirqd_routing" = "0x8b"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x80"
-
-			register "alt_gp_smi_en" = "0x0000"
-			register "gpe0_en_1" = "0x00000000"
-			register "gpe0_en_2" = "0x00000000"
-			register "gpe0_en_3" = "0x00000000"
-			register "gpe0_en_4" = "0x00000000"
-
-			register "ide_legacy_combined" = "0x0"
-			register "sata_ahci" = "0x1"
-			register "sata_port_map" = "0x2"
-
-			device pci 13.0 on end # Smart Sound Audio DSP
-			device pci 14.0 on end # USB3 XHCI
-			device pci 15.0 off end # Serial I/O DMA
-			device pci 15.1 off end # I2C0
-			device pci 15.2 off end # I2C1
-			device pci 15.3 off end # GSPI0
-			device pci 15.4 off end # GSPI1
-			device pci 15.5 off end # UART0
-			device pci 15.6 off end # UART1
-			device pci 16.0 on end # Management Engine Interface 1
-			device pci 16.1 off end # Management Engine Interface 2
-			device pci 16.2 off end # Management Engine IDE-R
-			device pci 16.3 off end # Management Engine KT
-			device pci 17.0 off end # SDIO
-			device pci 19.0 on end # GbE
-			device pci 1b.0 on end # High Definition Audio
-			device pci 1c.0 on end # PCIe Port #1
-			device pci 1c.1 on end # PCIe Port #2
-			device pci 1c.2 on end # PCIe Port #3
-			device pci 1c.3 on end # PCIe Port #4
-			device pci 1c.4 on end # PCIe Port #5
-			device pci 1c.5 on end # PCIe Port #6
-			device pci 1d.0 on end # USB2 EHCI
-			device pci 1e.0 off end # PCI bridge
-			device pci 1f.0 on end # LPC bridge
-			device pci 1f.2 on end # SATA Controller
-			device pci 1f.3 on end # SMBus
-			device pci 1f.6 on end # Thermal
-		end
-	end
-end
diff --git a/src/mainboard/intel/wtm1/dsdt.asl b/src/mainboard/intel/wtm1/dsdt.asl
deleted file mode 100644
index 81e39c324d..0000000000
--- a/src/mainboard/intel/wtm1/dsdt.asl
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define ENABLE_TPM
-
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0
-	"COREv4",	// OEM id
-	"COREBOOT",     // OEM table id
-	0x20110725	// OEM revision
-)
-{
-	// Some generic macros
-	#include "acpi/platform.asl"
-
-	// global NVS and variables
-	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
-
-	// General Purpose Events
-	//#include "acpi/gpe.asl"
-
-	#include "acpi/thermal.asl"
-
-	#include "../../../cpu/intel/haswell/acpi/cpu.asl"
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <northbridge/intel/haswell/acpi/haswell.asl>
-			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
-		}
-	}
-
-	#include "acpi/chromeos.asl"
-	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
-
-	/* Chipset specific sleep states */
-	#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
-}
diff --git a/src/mainboard/intel/wtm1/fadt.c b/src/mainboard/intel/wtm1/fadt.c
deleted file mode 100644
index 7afbbfa698..0000000000
--- a/src/mainboard/intel/wtm1/fadt.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = get_pmbase();
-
-	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
-	memcpy(header->signature, "FACP", 4);
-	header->length = sizeof(acpi_fadt_t);
-	header->revision = 3;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 1;
-
-	fadt->firmware_ctrl = (unsigned long) facs;
-	fadt->dsdt = (unsigned long) dsdt;
-	fadt->model = 1;
-	fadt->preferred_pm_profile = PM_MOBILE;
-
-	fadt->sci_int = 0x9;
-	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
-	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0;
-
-	fadt->pm1a_evt_blk = pmbase;
-	fadt->pm1b_evt_blk = 0x0;
-	fadt->pm1a_cnt_blk = pmbase + 0x4;
-	fadt->pm1b_cnt_blk = 0x0;
-	fadt->pm2_cnt_blk = pmbase + 0x50;
-	fadt->pm_tmr_blk = pmbase + 0x8;
-	fadt->gpe0_blk = pmbase + 0x80;
-	fadt->gpe1_blk = 0;
-
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 32;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-	fadt->cst_cnt = 0;
-	fadt->p_lvl2_lat = 1;
-	fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 0;
-	fadt->day_alrm = 0xd;
-	fadt->mon_alrm = 0x00;
-	fadt->century = 0x00;
-	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
-
-	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
-			ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
-			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
-	fadt->reset_reg.space_id = 1;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0;
-
-	fadt->reset_value = 6;
-	fadt->x_firmware_ctl_l = (unsigned long)facs;
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (unsigned long)dsdt;
-	fadt->x_dsdt_h = 0;
-
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = pmbase;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 0;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 0;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 8;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	fadt->x_gpe0_blk.space_id = 0;
-	fadt->x_gpe0_blk.bit_width = 0;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = 0;
-	fadt->x_gpe0_blk.addrh = 0x0;
-
-	fadt->x_gpe1_blk.space_id = 1;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0x0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum =
-	    acpi_checksum((void *) fadt, header->length);
-}
diff --git a/src/mainboard/intel/wtm1/gpio.h b/src/mainboard/intel/wtm1/gpio.h
deleted file mode 100644
index 9f813d6b8a..0000000000
--- a/src/mainboard/intel/wtm1/gpio.h
+++ /dev/null
@@ -1,371 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef INTEL_WTM1_GPIO_H
-#define INTEL_WTM1_GPIO_H
-
-#include "southbridge/intel/lynxpoint/lp_gpio.h"
-
-const struct pch_lp_gpio_map mainboard_gpio_map[] = {
-	/* UART1_RXD */
-	{ .gpio  = 0,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* UART1_TXD */
-	{ .gpio  = 1,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* UART1_RTSD */
-	{ .gpio  = 2,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* UART1_CTSB */
-	{ .gpio  = 3,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* I2C0_SDA */
-	{ .gpio  = 4,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* I2C0_SCL */
-	{ .gpio  = 5,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* I2C1_SDA */
-	{ .gpio  = 6,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* I2C1_SCL */
-	{ .gpio  = 7,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* PCIE_SLOT3_WAKE_R_N / ICC_EN_N */
-	{ .gpio  = 8,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* PCH_GPIO9 / XDP_FN5 */
-	{ .gpio  = 9,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* PCH_GPIO10 / XDP_FN6 */
-	{ .gpio  = 10,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* SMBALERTB / PCH_GPIO11 / AMB_THRM_R_N */
-	{ .gpio  = 11,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* PM_LANPHY_ENABLE */
-	{ .gpio  = 12,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* USB30_P0_PWREN */
-	{ .gpio  = 13,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* SENSOR_HUB_INT_R_N */
-	{ .gpio  = 14,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE,
-	  .conf1 = GPIO_SENSE_ENABLE,
-	  .owner = GPIO_OWNER_GPIO,
-	  .irqen = GPIO_IRQ_ENABLE },
-	/* HOST_ALERT1_R_N */
-	{ .gpio  = 15,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* LAN_RST_N */
-	{ .gpio  = 16,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* CRIT_TEMP_REP_N */
-	{ .gpio  = 17,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW },
-	/* SRC0CLKRQB */
-	{ .gpio  = 18,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SRC1CLKRQB */
-	{ .gpio  = 19,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SRC2CLKRQB */
-	{ .gpio  = 20,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SRC3CLKRQB */
-	{ .gpio  = 21,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SRC4CLKRQB_TRST2 */
-	{ .gpio  = 22,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* SRC5CLKRQB_TDI2 */
-	{ .gpio  = 23,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* BT_ALERT_ME_LED */
-	{ .gpio  = 24,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT },
-	/* USB_WAKEOUT_N / USB2_4_5_PWREN */
-	{ .gpio  = 25,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* NFC_IRQ_MGP5 */
-	{ .gpio  = 26,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE,
-	  .conf1 = GPIO_SENSE_ENABLE,
-	  .owner = GPIO_OWNER_GPIO,
-	  .irqen = GPIO_IRQ_ENABLE },
-	/* SMC_WAKE_SCI_N */
-	{ .gpio  = 27,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT,
-	  .conf1 = GPIO_SENSE_ENABLE },
-	/* PCH_NFC_RESET_CMNHDR */
-	{ .gpio  = 28,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* SLP_WLANB */
-	{ .gpio  = 29,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SUSWARNB_SUSPWRDNACK_MGPIO1 */
-	{ .gpio  = 30,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* ACPRESENT_MGPIO2 */
-	{ .gpio  = 31,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* CLKRUNB */
-	{ .gpio  = 32,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SATA0_PHYSLP */
-	{ .gpio  = 33,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SMC_EXTSMI_R_N */
-	{ .gpio  = 34,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT },
-	/* SATA_DIRECT_ODD_PRSNT_R_N */
-	{ .gpio  = 35,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* CMNHDR_PEDET2 */
-	{ .gpio  = 36,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT },
-	/* MSATA_MPCIE_DET_N */
-	{ .gpio  = 37,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SATA1_PHYSLP_DIRECT */
-	{ .gpio  = 38,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SATA2_PHYSLP_CMNHDR */
-	{ .gpio  = 39,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* USB_OC_0_1_R_N */
-	{ .gpio  = 40,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* USB_OC_6_7_R_N */
-	{ .gpio  = 41,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* USB_OC_4_5_R_N */
-	{ .gpio  = 42,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* USB32_P1_PWREN */
-	{ .gpio  = 43,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* SNSR_HUB_RST_N */
-	{ .gpio  = 44,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* PCIE_SLOT4_WAKE_N */
-	{ .gpio  = 45,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT },
-	/* SNSR_HUB_PWREN_N */
-	{ .gpio  = 46,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* SPI_TPM_HDR_IRQ_N */
-	{ .gpio  = 47,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT,
-	  .conf1 = GPIO_SENSE_ENABLE,
-	  .owner = GPIO_OWNER_GPIO,
-	  .irqen = GPIO_IRQ_ENABLE },
-	/* SLOT5_RST_GYRO_INT2_N */
-	{ .gpio  = 48,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* GPS_EN_NGFF_ALS_INT_N */
-	{ .gpio  = 49,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT,
-	  .conf1 = GPIO_SENSE_ENABLE,
-	  .owner = GPIO_OWNER_GPIO,
-	  .irqen = GPIO_IRQ_ENABLE },
-	/* TOUCH_PANEL_INTR_N */
-	{ .gpio  = 50,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT,
-	  .conf1 = GPIO_SENSE_ENABLE,
-	  .owner = GPIO_OWNER_GPIO,
-	  .irqen = GPIO_IRQ_ENABLE },
-	/* PCIE_SLOT5_WAKE_R_N */
-	{ .gpio  = 51,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT },
-	/* GYRO_INT1_CLV / TOUCH_RST_N */
-	{ .gpio  = 52,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* CODEC_IRQ */
-	{ .gpio  = 53,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT,
-	  .conf1 = GPIO_SENSE_ENABLE,
-	  .owner = GPIO_OWNER_GPIO,
-	  .irqen = GPIO_IRQ_ENABLE },
-	/* PCH_MC_WAKE_R_N */
-	{ .gpio  = 54,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT },
-	/* THCP_INTR_N */
-	{ .gpio  = 55,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT,
-	  .conf1 = GPIO_SENSE_ENABLE,
-	  .owner = GPIO_OWNER_GPIO,
-	  .irqen = GPIO_IRQ_ENABLE },
-	/* PCIE_SLOT4_RST_N */
-	{ .gpio  = 56,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* PCIE_SLOT4_PWREN_N */
-	{ .gpio  = 57,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* SPI_TPM_HDR_PWREN_N */
-	{ .gpio  = 58,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* PCIE_SLOT3_RST_N */
-	{ .gpio  = 59,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* PCIE_SLOT3_PWREN_N */
-	{ .gpio  = 60,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* SUS_STATB */
-	{ .gpio  = 61,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SUSCLK */
-	{ .gpio  = 62,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SLP_S5B */
-	{ .gpio  = 63,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SDIO_CLK */
-	{ .gpio  = 64,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SDIO_CMD */
-	{ .gpio  = 65,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SDIO_D0 */
-	{ .gpio  = 66,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SDIO_D1 */
-	{ .gpio  = 67,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SDIO_D2 */
-	{ .gpio  = 68,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SDIO_D3 */
-	{ .gpio  = 69,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* LPSS_SDIO_VDD_EN_CMNHDR_R */
-	{ .gpio  = 70,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* MPHY_PWREN */
-	{ .gpio  = 71,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* PM_BATLOW_R_N */
-	{ .gpio  = 72,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* PCH_GP73_MGP8 / PCH_HOT_N */
-	{ .gpio  = 73,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SML1_DATA */
-	{ .gpio  = 74,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* SML1_DATA */
-	{ .gpio  = 75,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* PCH_AUDIO_PWR_N */
-	{ .gpio  = 76,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* MPCIE_RST_N */
-	{ .gpio  = 77,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* EXTTS_SNI_DRV0_PCH */
-	{ .gpio  = 78,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT },
-	/* SIO1007_IRQ_N */
-	{ .gpio  = 79,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE,
-	  .conf1 = GPIO_SENSE_ENABLE,
-	  .owner = GPIO_OWNER_ACPI,
-	  .route = GPIO_ROUTE_SCI,
-	  .irqen = GPIO_IRQ_ENABLE },
-	/* EXTTS_SNI_DRV1_PCH */
-	{ .gpio  = 80,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT },
-	/* SPKR */
-	{ .gpio  = 81,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* RCINB */
-	{ .gpio  = 82,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* MC_3.3_PWREN_N */
-	{ .gpio  = 83,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* PCIE_SLOT5_PWREN_N */
-	{ .gpio  = 84,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* MC_1.5_PWREN_N */
-	{ .gpio  = 85,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* SATA_ODD_PWRGT_R */
-	{ .gpio  = 86,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* PECI_HDR / PCH_RF_KILL_N */
-	{ .gpio  = 87,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* TCHP_PWREN_N */
-	{ .gpio  = 88,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* TOUCH_PWREN_N */
-	{ .gpio  = 89,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* SATA1_PWR_EN_N  */
-	{ .gpio  = 90,
-	  .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW,
-	  .conf1 = GPIO_SENSE_DISABLE },
-	/* UART0_RXD */
-	{ .gpio  = 91,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* UART0_TXD */
-	{ .gpio  = 92,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* UART0_RTSB */
-	{ .gpio  = 93,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* UART0_CTSB */
-	{ .gpio  = 94,
-	  .conf0 = GPIO_MODE_NATIVE },
-	/* END */
-	{ .gpio  = GPIO_LIST_END }
-};
-
-#endif
diff --git a/src/mainboard/intel/wtm1/hda_verb.h b/src/mainboard/intel/wtm1/hda_verb.h
deleted file mode 100644
index c34d0f57c7..0000000000
--- a/src/mainboard/intel/wtm1/hda_verb.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-static const u32 mainboard_cim_verb_data[] = {
-	/* coreboot specific header */
-	0x10134210,	// Codec Vendor / Device ID: Cirrus Logic CS4210
-	0x10134210,	// Subsystem ID
-	0x00000007,	// Number of jacks
-
-	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10134210 */
-	0x00172010,
-	0x00172142,
-	0x00172213,
-	0x00172310,
-
-	/* Pin Widget Verb Table */
-
-	/* Pin Complex (NID 0x05)     1/8   Gray  HP Out at Ext Front */
-	0x00571cf0,
-	0x00571d20,
-	0x00571e21,
-	0x00571f02,
-
-	/* Pin Complex (NID 0x06)  Analog Unknown  Speaker at Int N/A */
-	0x00671c10,
-	0x00671d00,
-	0x00671e17,
-	0x00671f90,
-
-	/* Pin Complex (NID 0x07)     1/8    Grey  Line In at Ext Front */
-	0x00771cf0,
-	0x00771d20,
-	0x00771ea1,
-	0x00771f02,
-
-	/* Pin Complex (NID 0x08)  Analog Unknown  Mic at Oth Mobile-In */
-	0x00871c37,
-	0x00871d00,
-	0x00871ea7,
-	0x00871f77,
-
-	/* Pin Complex (NID 0x09) Digital Unknown  Mic at Oth Mobile-In */
-	0x00971c3e,
-	0x00971d00,
-	0x00971ea6,
-	0x00971f77,
-
-	/* Pin Complex (NID 0x0a) Optical   Black  SPDIF Out at Ext N/A */
-	0x00a71cf0,
-	0x00a71d10,
-	0x00a71e45,
-	0x00a71f43,
-
-	/* coreboot specific header */
-	0x80862805,	// Codec Vendor / Device ID: Intel CougarPoint HDMI
-	0x80860101,	// Subsystem ID
-	0x00000004,	// Number of jacks
-
-	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
-	0x00172001,
-	0x00172101,
-	0x00172286,
-	0x00172380,
-
-	/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
-	0x30571c10,
-	0x30571d00,
-	0x30571e56,
-	0x30571f18,
-
-	/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
-	0x30671c20,
-	0x30671d00,
-	0x30671e56,
-	0x30671f18,
-
-	/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
-	0x30771c30,
-	0x30771d00,
-	0x30771e56,
-	0x30771f18
-};
-
diff --git a/src/mainboard/intel/wtm1/mainboard.c b/src/mainboard/intel/wtm1/mainboard.c
deleted file mode 100644
index f5b00546f7..0000000000
--- a/src/mainboard/intel/wtm1/mainboard.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <string.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
-#include <x86emu/x86emu.h>
-#endif
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
-#include "hda_verb.h"
-#include <southbridge/intel/lynxpoint/pch.h>
-
-void mainboard_suspend_resume(void)
-{
-	/* Call SMM finalize() handlers before resume */
-	outb(0xcb, 0xb2);
-}
-
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-static int int15_handler(struct eregs *regs)
-{
-	int res=-1;
-
-	printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
-			__func__, regs->eax & 0xffff);
-
-	switch(regs->eax & 0xffff) {
-	case 0x5f34:
-		/*
-		 * Set Panel Fitting Hook:
-		 *  bit 2 = Graphics Stretching
-		 *  bit 1 = Text Stretching
-		 *  bit 0 = Centering (do not set with bit1 or bit2)
-		 *  0     = video bios default
-		 */
-		regs->eax &= 0xffff0000;
-		regs->eax |= 0x005f;
-		regs->ecx &= 0xffffff00;
-		regs->ecx |= 0x01;
-		res = 0;
-		break;
-	case 0x5f35:
-		/*
-		 * Boot Display Device Hook:
-		 *  bit 0 = CRT
-		 *  bit 1 = TV (eDP) *
-		 *  bit 2 = EFP *
-		 *  bit 3 = LFP
-		 *  bit 4 = CRT2
-		 *  bit 5 = TV2 (eDP) *
-		 *  bit 6 = EFP2 *
-		 *  bit 7 = LFP2
-		 */
-		regs->eax &= 0xffff0000;
-		regs->eax |= 0x005f;
-		regs->ecx &= 0xffff0000;
-		regs->ecx |= 0x0000;
-		res = 0;
-		break;
-	case 0x5f51:
-		/*
-		 * Hook to select active LFP configuration:
-		 *  00h = No LVDS, VBIOS does not enable LVDS
-		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
-		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
-		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
-		 */
-		regs->eax &= 0xffff0000;
-		regs->eax |= 0x005f;
-		regs->ecx &= 0xffff0000;
-		regs->ecx |= 0x0003;
-		res = 0;
-		break;
-	case 0x5f70:
-		switch ((regs->ecx >> 8) & 0xff) {
-		case 0:
-			/* Get Mux */
-			regs->eax &= 0xffff0000;
-			regs->eax |= 0x005f;
-			regs->ecx &= 0xffff0000;
-			regs->ecx |= 0x0000;
-			res = 0;
-			break;
-		case 1:
-			/* Set Mux */
-			regs->eax &= 0xffff0000;
-			regs->eax |= 0x005f;
-			regs->ecx &= 0xffff0000;
-			regs->ecx |= 0x0000;
-			res = 0;
-			break;
-		case 2:
-			/* Get SG/Non-SG mode */
-			regs->eax &= 0xffff0000;
-			regs->eax |= 0x005f;
-			regs->ecx &= 0xffff0000;
-			regs->ecx |= 0x0000;
-			res = 0;
-			break;
-		default:
-			/* Interrupt was not handled */
-			printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
-				((regs->ecx >> 8) & 0xff));
-			return 0;
-		}
-		break;
-
-        default:
-		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
-				regs->eax & 0xffff);
-		break;
-	}
-	return res;
-}
-#endif
-
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
-static int int15_handler(void)
-{
-	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
-			  __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
-
-	switch (M.x86.R_AX) {
-	case 0x5f34:
-		/*
-		 * Set Panel Fitting Hook:
-		 *  bit 2 = Graphics Stretching
-		 *  bit 1 = Text Stretching
-		 *  bit 0 = Centering (do not set with bit1 or bit2)
-		 */
-		M.x86.R_AX = 0x005f;
-		M.x86.R_CX = 0x0001;
-		break;
-	case 0x5f35:
-		/*
-		 * Boot Display Device Hook:
-		 *  bit 0 = CRT
-		 *  bit 1 = TV (eDP) *
-		 *  bit 2 = EFP *
-		 *  bit 3 = LFP
-		 *  bit 4 = CRT2
-		 *  bit 5 = TV2 (eDP) *
-		 *  bit 6 = EFP2 *
-		 *  bit 7 = LFP2
-		 */
-		M.x86.R_AX = 0x005f;
-		M.x86.R_CX = 0x0000;
-		break;
-	case 0x5f51:
-		/*
-		 * Hook to select active LFP configuration:
-		 *  00h = No LVDS, VBIOS does not enable LVDS
-		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
-		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
-		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
-		 */
-		M.x86.R_AX = 0x005f;
-		M.x86.R_CX = 3;
-		break;
-	case 0x5f70:
-		/* Unknown */
-		M.x86.R_AX = 0x005f;
-		M.x86.R_CX = 0;
-		break;
-	default:
-		/* Interrupt was not handled */
-		printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
-			M.x86.R_AX);
-		return 0;
-	}
-
-	/* Interrupt handled */
-	return 1;
-}
-#endif
-
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-static void int15_install(void)
-{
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-	typedef int (* yabel_handleIntFunc)(void);
-	extern yabel_handleIntFunc yabel_intFuncArray[256];
-	yabel_intFuncArray[0x15] = int15_handler;
-#endif
-#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-	mainboard_interrupt_handlers(0x15, &int15_handler);
-#endif
-}
-#endif
-
-/* Audio Setup */
-
-extern const u32 * cim_verb_data;
-extern u32 cim_verb_data_size;
-
-static void verb_setup(void)
-{
-	cim_verb_data = mainboard_cim_verb_data;
-	cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
-
-static void mainboard_enable(device_t dev)
-{
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-	/* Install custom int15 handler for VGA OPROM */
-	int15_install();
-#endif
-	verb_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
-
diff --git a/src/mainboard/intel/wtm1/mainboard_smi.c b/src/mainboard/intel/wtm1/mainboard_smi.c
deleted file mode 100644
index 3ffc68441d..0000000000
--- a/src/mainboard/intel/wtm1/mainboard_smi.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/me.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <cpu/intel/haswell/haswell.h>
-
-int mainboard_io_trap_handler(int smif)
-{
-	switch (smif) {
-	case 0x99:
-		printk(BIOS_DEBUG, "Sample\n");
-		smm_get_gnvs()->smif = 0;
-		break;
-	default:
-		return 0;
-	}
-
-	/* On success, the IO Trap Handler returns 0
-	 * On failure, the IO Trap Handler returns a value != 0
-	 *
-	 * For now, we force the return value to 0 and log all traps to
-	 * see what's going on.
-	 */
-	//gnvs->smif = 0;
-	return 1;
-}
-
-#define APMC_FINALIZE 0xcb
-
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 apmc)
-{
-	switch (apmc) {
-	case APMC_FINALIZE:
-		if (mainboard_finalized) {
-			printk(BIOS_DEBUG, "SMI#: Already finalized\n");
-			return 0;
-		}
-
-		intel_me_finalize_smm();
-		intel_pch_finalize_smm();
-		intel_northbridge_haswell_finalize_smm();
-		intel_cpu_haswell_finalize_smm();
-
-		mainboard_finalized = 1;
-		break;
-	}
-	return 0;
-}
diff --git a/src/mainboard/intel/wtm1/romstage.c b/src/mainboard/intel/wtm1/romstage.c
deleted file mode 100644
index 525bd6ff49..0000000000
--- a/src/mainboard/intel/wtm1/romstage.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <console/console.h>
-#include "cpu/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/raminit.h"
-#include "southbridge/intel/lynxpoint/pch.h"
-#include "southbridge/intel/lynxpoint/lp_gpio.h"
-#include "gpio.h"
-
-const struct rcba_config_instruction rcba_config[] = {
-
-	/*
-	 *             GFX    INTA -> PIRQA (MSI)
-	 * D28IP_P1IP  WLAN   INTA -> PIRQB
-	 * D28IP_P4IP  ETH0   INTB -> PIRQC
-	 * D29IP_E1P   EHCI1  INTA -> PIRQD
-	 * D20IP_XHCI  XHCI   INTA -> PIRQA
-	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
-	 * D31IP_SMIP  SMBUS  INTB -> PIRQG
-	 * D31IP_TTIP  THRT   INTC -> PIRQH
-	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
-	 */
-
-	/* Device interrupt pin register (board specific) */
-	RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
-			(INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
-	RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
-	RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
-			(INTB << D28IP_P4IP)),
-	RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
-	RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
-	RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)),
-	RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
-	RCBA_SET_REG_32(D20IR, (INTA << D20IP_XHCI)),
-
-	/* Device interrupt route registers */
-	RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)),
-	RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)),
-	RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)),
-	RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)),
-	RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),
-	RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
-	RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
-	RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
-	RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
-	RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQA, 0, 0, 0)),
-
-	/* Disable unused devices (board specific) */
-	RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
-
-	RCBA_END_CONFIG,
-};
-
-void mainboard_romstage_entry(unsigned long bist)
-{
-	struct pei_data pei_data = {
-		pei_version: PEI_VERSION,
-		mchbar: DEFAULT_MCHBAR,
-		dmibar: DEFAULT_DMIBAR,
-		epbar: DEFAULT_EPBAR,
-		pciexbar: DEFAULT_PCIEXBAR,
-		smbusbar: SMBUS_IO_BASE,
-		wdbbar: 0x4000000,
-		wdbsize: 0x1000,
-		hpet_address: HPET_ADDR,
-		rcba: DEFAULT_RCBA,
-		pmbase: DEFAULT_PMBASE,
-		gpiobase: DEFAULT_GPIOBASE,
-		temp_mmio_base: 0xfed08000,
-		system_type: 5, /* ULT */
-		tseg_size: CONFIG_SMM_TSEG_SIZE,
-		spd_addresses: { 0xa0, 0xa2, 0xa4, 0xa6 },
-		ec_present: 1,
-		// 0 = leave channel enabled
-		// 1 = disable dimm 0 on channel
-		// 2 = disable dimm 1 on channel
-		// 3 = disable dimm 0+1 on channel
-		dimm_channel0_disabled: 2,
-		dimm_channel1_disabled: 2,
-		max_ddr3_freq: 1600,
-		usb_port_config: {
-			{ 1, 0, 0x0040 }, /* P0: */
-			{ 1, 0, 0x0040 }, /* P1: */
-			{ 1, 0, 0x0040 }, /* P2: */
-			{ 1, 0, 0x0040 }, /* P3: */
-			{ 1, 0, 0x0040 }, /* P4: */
-			{ 1, 0, 0x0040 }, /* P5: */
-			{ 1, 0, 0x0040 }, /* P6: */
-			{ 1, 0, 0x0040 }, /* P7: */
-			{ 1, 0, 0x0040 }, /* P8: */
-			{ 1, 0, 0x0040 }, /* P9: */
-			{ 1, 0, 0x0040 }, /* P10: */
-			{ 1, 0, 0x0000 }, /* P11: */
-			{ 1, 0, 0x0040 }, /* P12: */
-			{ 1, 0, 0x0040 }, /* P13: */
-		},
-	};
-
-	struct romstage_params romstage_params = {
-		.pei_data = &pei_data,
-		.gpio_map = &mainboard_gpio_map,
-		.rcba_config = &rcba_config[0],
-		.bist = bist,
-	};
-
-	/* Call into the real romstage main with this board's attributes. */
-	romstage_common(&romstage_params);
-}
diff --git a/src/mainboard/intel/wtm1/thermal.h b/src/mainboard/intel/wtm1/thermal.h
deleted file mode 100644
index e6116b6f5d..0000000000
--- a/src/mainboard/intel/wtm1/thermal.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef WTM2_THERMAL_H
-#define WTM2_THERMAL_H
-
-/* Fan is OFF */
-#define FAN4_THRESHOLD_OFF	0
-#define FAN4_THRESHOLD_ON	0
-#define FAN4_PWM		0x00
-
-/* Fan is at LOW speed */
-#define FAN3_THRESHOLD_OFF	48
-#define FAN3_THRESHOLD_ON	55
-#define FAN3_PWM		0x40
-
-/* Fan is at MEDIUM speed */
-#define FAN2_THRESHOLD_OFF	52
-#define FAN2_THRESHOLD_ON	64
-#define FAN2_PWM		0x80
-
-/* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF	60
-#define FAN1_THRESHOLD_ON	68
-#define FAN1_PWM		0xb0
-
-/* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF	66
-#define FAN0_THRESHOLD_ON	78
-#define FAN0_PWM		0xff
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE	100
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE	90
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE		100
-
-#endif