diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2021-04-16 13:08:38 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-23 14:49:31 +0000 |
| commit | d742d02fe2fff0446d62d0430e1d1ba2b88cbf0a (patch) | |
| tree | bca9f4b366db6a3e2a3884942b28df9b6ad5f924 /src/mainboard/intel | |
| parent | 9452aab4d3656eca479b1f1c0ff4350ea2d04978 (diff) | |
| download | coreboot-d742d02fe2fff0446d62d0430e1d1ba2b88cbf0a.tar.xz | |
mb/intel/shadowmountain: Enable HECI1 interface
The patch enables HECI1 interface
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia2638559bcaac78d024e35abd09534b61eacb843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 7b0edadccb..beaf8fd1ec 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -268,7 +268,7 @@ chip soc/intel/alderlake end end # I2C2 device pci 15.3 on end # I2C3 - device pci 16.0 off end # HECI1 + device pci 16.0 on end # HECI1 device pci 16.1 off end # HECI2 device pci 16.2 off end # CSME device pci 16.3 off end # CSME |