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authorPatrick Rudolph <siro@das-labor.org>2016-02-06 17:42:42 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2016-02-18 01:35:57 +0100
commite8e66f47631c505ab153d8a348058350b9acfe88 (patch)
tree535bc168855923222affbf6bdb06620cbd8fb343 /src/mainboard/intel
parentffc31d07f7839fa72073aae4ddbbd025ac4a7bac (diff)
downloadcoreboot-e8e66f47631c505ab153d8a348058350b9acfe88.tar.xz
southbridge/intel/bd82x6x: Use common gpio.c
Use shared gpio code from common folder. Bd82x6x's gpio.c and gpio.h is used by other southbridges as well and will be removed once it is unused. Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13614 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/emeraldlake2/chromeos.c25
-rw-r--r--src/mainboard/intel/emeraldlake2/gpio.c2
-rw-r--r--src/mainboard/intel/emeraldlake2/romstage.c1
3 files changed, 6 insertions, 22 deletions
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index 98749e0c6e..bb4ebe9f54 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
@@ -81,30 +82,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_developer_mode_switch(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
- u32 gp_lvl2 = inl(gpio_base + 0x38);
-
- /* Developer: GPIO17, active high */
- return (gp_lvl2 >> (57-32)) & 1;
+ /* Developer: GPIO57, active high */
+ return get_gpio(57);
}
int get_recovery_mode_switch(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
- u32 gp_lvl = inl(gpio_base + 0x0c);
-
/* Recovery: GPIO22, active low */
- return !((gp_lvl >> 22) & 1);
+ return !get_gpio(22);
}
diff --git a/src/mainboard/intel/emeraldlake2/gpio.c b/src/mainboard/intel/emeraldlake2/gpio.c
index 37b2430aea..050d44e491 100644
--- a/src/mainboard/intel/emeraldlake2/gpio.c
+++ b/src/mainboard/intel/emeraldlake2/gpio.c
@@ -16,7 +16,7 @@
#ifndef EMERALDLAKE2_GPIO_H
#define EMERALDLAKE2_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 2752778047..069b6adb35 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -31,6 +31,7 @@
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>