Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

27 files changed, 120 insertions, 120 deletions

diff --git a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
index 93e4b87fee..de2ec481fb 100644
--- a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
+++ b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/* This is board specific information: IRQ routing for the 
+/* This is board specific information: IRQ routing for the
  * i945
  */
 
diff --git a/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl
index b3b60d6ece..931fbfdeb4 100644
--- a/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl
+++ b/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl
@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/* This is board specific information: IRQ routing for the 
+/* This is board specific information: IRQ routing for the
  * 0:1e.0 PCI bridge of the ICH7
  */
 
diff --git a/src/mainboard/intel/d945gclf/acpi/mainboard.asl b/src/mainboard/intel/d945gclf/acpi/mainboard.asl
index 3d1ad0ea29..d321771c0a 100644
--- a/src/mainboard/intel/d945gclf/acpi/mainboard.asl
+++ b/src/mainboard/intel/d945gclf/acpi/mainboard.asl
@@ -28,7 +28,7 @@ Device (SLPB)
 Device (PWRB)
 {
 	Name(_HID, EisaId("PNP0C0C"))
-	
+
 	// Wake
 	Name(_PRW, Package(){0x1d, 0x04})
 }
diff --git a/src/mainboard/intel/d945gclf/acpi/platform.asl b/src/mainboard/intel/d945gclf/acpi/platform.asl
index 7c5b9da429..0a7930a3cc 100644
--- a/src/mainboard/intel/d945gclf/acpi/platform.asl
+++ b/src/mainboard/intel/d945gclf/acpi/platform.asl
@@ -42,9 +42,9 @@ Method(TRAP, 1, Serialized)
 	Return (SMIF)		// Return value of SMI handler
 }
 
-/* The _PIC method is called by the OS to choose between interrupt 
+/* The _PIC method is called by the OS to choose between interrupt
  * routing via the i8259 interrupt controller or the APIC.
- * 
+ *
  * _PIC is called with a parameter of 0 for i8259 configuration and
  * with a parameter of 1 for Local Apic/IOAPIC configuration.
  */
@@ -74,12 +74,12 @@ Method(_WAK,1)
 	// Notify PCI Express slots in case a card
 	// was inserted while a sleep state was active.
 
-	// Are we going to S3? 
+	// Are we going to S3?
 	If (LEqual(Arg0, 3)) {
 		// ..
 	}
 
-	// Are we going to S4? 
+	// Are we going to S4?
 	If (LEqual(Arg0, 4)) {
 		// ..
 	}
diff --git a/src/mainboard/intel/d945gclf/acpi/thermal.asl b/src/mainboard/intel/d945gclf/acpi/thermal.asl
index fb9d940955..fc79a35f61 100644
--- a/src/mainboard/intel/d945gclf/acpi/thermal.asl
+++ b/src/mainboard/intel/d945gclf/acpi/thermal.asl
@@ -25,7 +25,7 @@ Scope (\_TZ)
 	{
 
 		// FIXME these could/should be read from the
-		// GNVS area, so they can be controlled by 
+		// GNVS area, so they can be controlled by
 		// coreboot
 		Name(TC1V, 0x04)
 		Name(TC2V, 0x03)
diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c
index b7f92114c5..afa695502f 100644
--- a/src/mainboard/intel/d945gclf/acpi_tables.c
+++ b/src/mainboard/intel/d945gclf/acpi_tables.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
diff --git a/src/mainboard/intel/d945gclf/chip.h b/src/mainboard/intel/d945gclf/chip.h
index 90e8c27999..4e1432de69 100644
--- a/src/mainboard/intel/d945gclf/chip.h
+++ b/src/mainboard/intel/d945gclf/chip.h
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2008 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout
index e99c43d79b..9997584a54 100644
--- a/src/mainboard/intel/d945gclf/cmos.layout
+++ b/src/mainboard/intel/d945gclf/cmos.layout
@@ -1,6 +1,6 @@
 #
 # This file is part of the coreboot project.
-# 
+#
 # Copyright (C) 2007-2008 coresystems GmbH
 #
 # This program is free software; you can redistribute it and/or
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index af5f22b302..01a0bc67a5 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -1,6 +1,6 @@
 ##
 ## This file is part of the coreboot project.
-## 
+##
 ## Copyright (C) 2007-2008 coresystems GmbH
 ##
 ## This program is free software; you can redistribute it and/or
@@ -25,7 +25,7 @@ chip northbridge/intel/i945
                 end
         end
 
-        device pci_domain 0 on 
+        device pci_domain 0 on
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
 		device pci 02.0 on end # vga controller
@@ -66,7 +66,7 @@ chip northbridge/intel/i945
                 	device pci 1d.3 on end # USB UHCI
                 	device pci 1d.7 on end # USB2 EHCI
                 	device pci 1e.0 on end # PCI bridge
-			#device pci 1e.2 off end # AC'97 Audio 
+			#device pci 1e.2 off end # AC'97 Audio
 			#device pci 1e.3 off end # AC'97 Modem
                         device pci 1f.0 on # LPC bridge
                                 chip superio/smsc/lpc47m15x
diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl
index 1b025994f0..bf57e74b21 100644
--- a/src/mainboard/intel/d945gclf/dsdt.asl
+++ b/src/mainboard/intel/d945gclf/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock(
 
 	// General Purpose Events
 	//#include "acpi/gpe.asl"
-	
+
 	// mainboard specific devices
 	#include "acpi/mainboard.asl"
 
diff --git a/src/mainboard/intel/d945gclf/mainboard_smi.c b/src/mainboard/intel/d945gclf/mainboard_smi.c
index fc4c508194..c07a24c399 100644
--- a/src/mainboard/intel/d945gclf/mainboard_smi.c
+++ b/src/mainboard/intel/d945gclf/mainboard_smi.c
@@ -23,7 +23,7 @@
 #include <cpu/x86/smm.h>
 #include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
 
-/* The southbridge SMI handler checks whether gnvs has a 
+/* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler
  */
 extern global_nvs_t *gnvs;
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index 5d57f3d743..62850ebf1c 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
 
 	/* Legacy Interrupts */
 
-	/* I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */	
+	/* I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2);
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index e3e5814d3e..45e9fb1341 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2008 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -105,7 +105,7 @@ static void ich7_enable_lpc(void)
 static void early_superio_config_lpc47m15x(void)
 {
 	device_t dev;
-	
+
 	dev=PNP_DEV(0x2e, LPC47M15X_SP1);
 	pnp_enter_conf_state(dev);
 
@@ -276,7 +276,7 @@ void main(unsigned long bist)
 
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
-	
+
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 	dump_spd_registers();
 #endif
@@ -286,8 +286,8 @@ void main(unsigned long bist)
 	/* Perform some initialization that must run before stage2 */
 	early_ich7_init();
 
-	/* This should probably go away. Until now it is required 
-	 * and mainboard specific 
+	/* This should probably go away. Until now it is required
+	 * and mainboard specific
 	 */
 	rcba_config();
 
@@ -331,7 +331,7 @@ void main(unsigned long bist)
 		 * memory completely, but that's a wonderful clean up task for another
 		 * day.
 		 */
-		if (resume_backup_memory) 
+		if (resume_backup_memory)
 			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 
 		/* Magic for S3 resume */
diff --git a/src/mainboard/intel/d945gclf/rtl8168.c b/src/mainboard/intel/d945gclf/rtl8168.c
index e278bcfb4e..04fd56ccb1 100644
--- a/src/mainboard/intel/d945gclf/rtl8168.c
+++ b/src/mainboard/intel/d945gclf/rtl8168.c
@@ -28,7 +28,7 @@
 static void nic_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n");
-	// Nothing to do yet, but this has to be here to keep 
+	// Nothing to do yet, but this has to be here to keep
 	// coreboot from trying to execute an option ROM.
 }
 
diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig
index 991fddf0e2..d04e79eafe 100644
--- a/src/mainboard/intel/eagleheights/Kconfig
+++ b/src/mainboard/intel/eagleheights/Kconfig
@@ -57,7 +57,7 @@ config MAX_CPUS
 	int
 	default 4
 	depends on BOARD_INTEL_EAGLEHEIGHTS
-	
+
 config MAX_PHYSICAL_CPUS
 	int
 	default 2
diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c
index b4f2a185b3..87c67b5964 100644
--- a/src/mainboard/intel/jarrell/debug.c
+++ b/src/mainboard/intel/jarrell/debug.c
@@ -5,7 +5,7 @@
 static void print_reg(unsigned char index)
 {
         unsigned char data;
-                                                                                
+
         outb(index, 0x2e);
         data = inb(0x2f);
 	print_debug("0x");
@@ -15,7 +15,7 @@ static void print_reg(unsigned char index)
 	print_debug("\n");
         return;
 }
-        
+
 static void xbus_en(void)
 {
         /* select the XBUS function in the SIO */
@@ -25,7 +25,7 @@ static void xbus_en(void)
         outb(0x01, 0x2f);
 	return;
 }
-                                                                        
+
 static void setup_func(unsigned char func)
 {
         /* select the function in the SIO */
@@ -43,27 +43,27 @@ static void setup_func(unsigned char func)
         print_reg(0x75);
         return;
 }
-                                                                                
+
 static void siodump(void)
 {
         int i;
         unsigned char data;
-       
+
 	 print_debug("\n*** SERVER I/O REGISTERS ***\n");
         for (i=0x10; i<=0x2d; i++) {
                 print_reg((unsigned char)i);
         }
-#if 0                                                                         
+#if 0
         print_debug("\n*** XBUS REGISTERS ***\n");
         setup_func(0x0f);
         for (i=0xf0; i<=0xff; i++) {
                 print_reg((unsigned char)i);
         }
-                                                                                
+
         print_debug("\n***  SERIAL 1 CONFIG REGISTERS ***\n");
         setup_func(0x03);
         print_reg(0xf0);
-                                                                                
+
         print_debug("\n***  SERIAL 2 CONFIG REGISTERS ***\n");
         setup_func(0x02);
         print_reg(0xf0);
@@ -82,13 +82,13 @@ static void siodump(void)
 	print_debug("\nGPDI 4: 0x");
 	print_debug_hex8(data);
 	print_debug("\n");
-	
-#if 0                                                                                
-                                                                                
+
+#if 0
+
         print_debug("\n***  WATCHDOG TIMER REGISTERS ***\n");
         setup_func(0x0a);
         print_reg(0xf0);
-                                                                                
+
         print_debug("\n***  FAN CONTROL REGISTERS ***\n");
         setup_func(0x09);
         print_reg(0xf0);
@@ -103,11 +103,11 @@ static void siodump(void)
         print_reg(0xf7);
         print_reg(0xfe);
         print_reg(0xff);
-                                                                                
+
         print_debug("\n***  HEALTH MONITORING & CONTROL REGISTERS ***\n");
         setup_func(0x14);
         print_reg(0xf0);
-#endif                                                                           
+#endif
         return;
 }
 
@@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev)
 static void print_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0, 0x1f, 0x7); 
+	for(dev = PCI_DEV(0, 0, 0);
+		dev <= PCI_DEV(0, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
@@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev)
 	int i;
 	print_debug_pci_dev(dev);
 	print_debug("\n");
-	
+
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
@@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev)
 {
 	int i;
 	unsigned long bar;
-	
+
 	print_debug("BAR 14 Dump\n");
-	
+
 	bar = pci_read_config32(dev, 0x14);
 	for(i = 0; i <= 0x300; i+=4) {
-#if 0		
+#if 0
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
 			print_debug_hex8(i);
 			print_debug_char(':');
 		}
 		val = pci_read_config8(dev, i);
-#endif		
+#endif
 		if((i%4)==0) {
 		print_debug("\n");
 		print_debug_hex16(i);
@@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev)
 static void dump_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0, 0x1f, 0x7); 
+	for(dev = PCI_DEV(0, 0, 0);
+		dev <= PCI_DEV(0, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
@@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
 		device = ctrl->channel0[i];
 		if (device) {
 			int j;
-			print_debug("dimm: "); 
-			print_debug_hex8(i); 
+			print_debug("dimm: ");
+			print_debug_hex8(i);
 			print_debug(".0: ");
 			print_debug_hex8(device);
 			for(j = 0; j < 256; j++) {
@@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
 		device = ctrl->channel1[i];
 		if (device) {
 			int j;
-			print_debug("dimm: "); 
-			print_debug_hex8(i); 
+			print_debug("dimm: ");
+			print_debug_hex8(i);
 			print_debug(".1: ");
 			print_debug_hex8(device);
 			for(j = 0; j < 256; j++) {
@@ -278,7 +278,7 @@ void dump_spd_registers(void)
         	print_debug("\n");
                 print_debug("dimm ");
 		print_debug_hex8(device);
-		
+
                 for(i = 0; (i < 256) ; i++) {
 	                unsigned char byte;
                         if ((i % 16) == 0) {
@@ -291,7 +291,7 @@ void dump_spd_registers(void)
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
 				 print_debug("\n");
-			         break; 
+			         break;
 			}
 			print_debug_hex8(status);
 			print_debug_char(' ');
@@ -311,7 +311,7 @@ void dump_ipmi_registers(void)
         	print_debug("\n");
                 print_debug("ipmi ");
 		print_debug_hex8(device);
-		
+
                 for(i = 0; (i < 8) ; i++) {
 	                unsigned char byte;
 			status = smbus_read_byte(device, 2);
@@ -319,7 +319,7 @@ void dump_ipmi_registers(void)
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
 				 print_debug("\n");
-			         break; 
+			         break;
 			}
 			print_debug_hex8(status);
 			print_debug_char(' ');
@@ -327,4 +327,4 @@ void dump_ipmi_registers(void)
 		device += SMBUS_MEM_DEVICE_INC;
 		print_debug("\n");
 	}
-}	
+}
diff --git a/src/mainboard/intel/jarrell/devicetree.cb b/src/mainboard/intel/jarrell/devicetree.cb
index 32f70e3e85..3a40899b29 100644
--- a/src/mainboard/intel/jarrell/devicetree.cb
+++ b/src/mainboard/intel/jarrell/devicetree.cb
@@ -1,9 +1,9 @@
 chip northbridge/intel/e7520
-	device pci_domain 0 on 
+	device pci_domain 0 on
 		device pci 00.0 on end
 		device pci 00.1 on end
 		device pci 01.0 on end
-		device pci 02.0 on 
+		device pci 02.0 on
 			chip southbridge/intel/pxhd # pxhd1
 				device pci 00.0 on end
 				device pci 00.1 on end
@@ -28,7 +28,7 @@ chip northbridge/intel/e7520
 					device pci 0c.0 on end
 				end
 			end
-			device pci 1f.0 on 
+			device pci 1f.0 on
 				chip superio/nsc/pc87427
 					device pnp 2e.0 off end
 					device pnp 2e.2 on
@@ -60,7 +60,7 @@ chip northbridge/intel/e7520
 			end
 			device pci 1f.1 on end
 			device pci 1f.2 off end
-			device pci 1f.3 on end 
+			device pci 1f.3 on end
 			device pci 1f.5 off end
 			device pci 1f.6 off end
 			register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
diff --git a/src/mainboard/intel/jarrell/jarrell_fixups.c b/src/mainboard/intel/jarrell/jarrell_fixups.c
index 7fb5a20dbb..1261e61046 100644
--- a/src/mainboard/intel/jarrell/jarrell_fixups.c
+++ b/src/mainboard/intel/jarrell/jarrell_fixups.c
@@ -21,7 +21,7 @@ static void mch_reset(void)
 		value = inl(base);
 		value |= (1 <<19);
 		outl(value, base);
-		
+
                 /* Pull GPIO 19 low */
                 value = inl(base + 0x0c);
                 value &= ~(1 << 19);
@@ -38,7 +38,7 @@ static void mainboard_set_e7520_pll(unsigned bits)
 
 	/* currently only handle the Jarrell/PC87427 case */
 	dev = PC87427_GPIO_DEV;
-		
+
 
 	pnp_set_logical_device(dev);
 	gpio_index = pnp_read_iobase(dev, 0x60);
@@ -66,7 +66,7 @@ static void mainboard_set_e7520_pll(unsigned bits)
 		// mch_reset();
 		full_reset();
 	}
-	return; 
+	return;
 }
 
 static void mainboard_set_e7520_leds(void)
@@ -77,7 +77,7 @@ static void mainboard_set_e7520_leds(void)
 
 	/* currently only handle the Jarrell/PC87427 case */
 	dev = PC87427_GPIO_DEV;
-		
+
 	pnp_set_logical_device(dev);
 
 	/* enable */
@@ -88,17 +88,17 @@ static void mainboard_set_e7520_leds(void)
 
 	/* Set auto mode for dimm leds and post */
 	outb(0xf0,0x2e);
-	outb(0x70,0x2f);	
+	outb(0x70,0x2f);
 	outb(0xf4,0x2e);
-	outb(0x30,0x2f);	
+	outb(0x30,0x2f);
 	outb(0xf5,0x2e);
-	outb(0x88,0x2f);	
+	outb(0x88,0x2f);
 	outb(0xf6,0x2e);
-	outb(0x00,0x2f);	
+	outb(0x00,0x2f);
 	outb(0xf7,0x2e);
-	outb(0x90,0x2f);	
+	outb(0x90,0x2f);
 	outb(0xf8,0x2e);
-	outb(0x00,0x2f);	
+	outb(0x00,0x2f);
 
 	/* Turn the leds off */
 	outb(0x00,0x88);
@@ -106,12 +106,12 @@ static void mainboard_set_e7520_leds(void)
 
 	/* Disable the ports */
 	outb(0xf5,0x2e);
-	outb(0x00,0x2f);	
+	outb(0x00,0x2f);
 	outb(0xf7,0x2e);
-	outb(0x00,0x2f);	
+	outb(0x00,0x2f);
 	outb(0xf4,0x2e);
-	outb(0x00,0x2f);	
-	
-	return; 
+	outb(0x00,0x2f);
+
+	return;
 }
 
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
index 73aa575540..1386c16183 100644
--- a/src/mainboard/intel/jarrell/mptable.c
+++ b/src/mainboard/intel/jarrell/mptable.c
@@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v)
 	mc->reserved = 0;
 
 	smp_write_processors(mc);
-	
+
 	{
 		device_t dev;
 
@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v)
 			}
 		}
 	}
-	
+
 	/* define bus and isa numbers */
 	for(bus_num = 0; bus_num < bus_isa; bus_num++) {
 		smp_write_bus(mc, bus_num, "PCI	  ");
@@ -165,7 +165,7 @@ static void *smp_write_config_table(void *v)
 			}
 		}
 	}
-	
+
 	/* ISA backward compatibility interrupts  */
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 		bus_isa, 0x00, 0x08, 0x00);
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index d3f6c7a707..823519984e 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -51,8 +51,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 static void main(unsigned long bist)
 {
 	/*
-	 * 
-	 * 
+	 *
+	 *
 	 */
 	static const struct mem_controller mch[] = {
 		{
@@ -117,7 +117,7 @@ static void main(unsigned long bist)
 	disable_watchdogs();
 	power_down_reset_check();
 //	dump_ipmi_registers();
-	mainboard_set_e7520_leds();	
+	mainboard_set_e7520_leds();
 	sdram_initialize(ARRAY_SIZE(mch), mch);
 	ich5_watchdog_on();
 #if 0
@@ -128,7 +128,7 @@ static void main(unsigned long bist)
 	dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
 
-#if 0 // temporarily disabled 
+#if 0 // temporarily disabled
 	/* Check the first 1M */
 //	ram_check(0x00000000, 0x000100000);
 //	ram_check(0x00000000, 0x000a0000);
@@ -138,9 +138,9 @@ static void main(unsigned long bist)
 #if 0
 	ram_check(0x00000000, 0x02000000);
 #endif
-	
+
 #endif
-#if 0	
+#if 0
 	while(1) {
 		hlt();
 	}
diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c
index 90782d9fbf..f7c42caa78 100644
--- a/src/mainboard/intel/jarrell/watchdog.c
+++ b/src/mainboard/intel/jarrell/watchdog.c
@@ -29,17 +29,17 @@ static void disable_ich5_watchdog(void)
 	value = pci_read_config16(dev, 0x04);
 	value |= (1 << 10);
 	pci_write_config16(dev, 0x04, value);
-	
+
 	/* Set and enable acpibase */
 	pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
 	pci_write_config8(dev, 0x44, 0x10);
 	base = ICH5_WDBASE + 0x60;
-	
+
 	/* Set bit 11 in TCO1_CNT */
 	value = inw(base + 0x08);
 	value |= 1 << 11;
 	outw(value, base + 0x08);
-	
+
 	/* Clear TCO timeout status */
 	outw(0x0008, base + 0x04);
 	outw(0x0002, base + 0x06);
@@ -83,7 +83,7 @@ static void disable_jarell_frb3(void)
 	outl(value, base + 0x38);
 	value &= ~(1 << 16);
 	outl(value, base + 0x38);
-				  
+
 }
 
 static void disable_watchdogs(void)
@@ -114,12 +114,12 @@ static void ich5_watchdog_on(void)
 	value = pci_read_config16(dev, 0x04);
 	value |= (1 << 10);
 	pci_write_config16(dev, 0x04, value);
-	
+
 	/* Set and enable acpibase */
 	pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
 	pci_write_config8(dev, 0x44, 0x10);
 	base = ICH5_WDBASE + 0x60;
-	
+
 	/* Clear TCO timeout status */
 	outw(0x0008, base + 0x04);
 	outw(0x0002, base + 0x06);
@@ -132,7 +132,7 @@ static void ich5_watchdog_on(void)
 	/* clear bit 11 in TCO1_CNT to start watchdog */
 	value = inw(base + 0x08);
 	value &= ~(1 << 11);
-	outw(value, base + 0x08);	
+	outw(value, base + 0x08);
 
 	print_debug("Watchdog ICH5 enabled\n");
 }
diff --git a/src/mainboard/intel/xe7501devkit/acpi_tables.c b/src/mainboard/intel/xe7501devkit/acpi_tables.c
index fd43eb693b..1188467f20 100644
--- a/src/mainboard/intel/xe7501devkit/acpi_tables.c
+++ b/src/mainboard/intel/xe7501devkit/acpi_tables.c
@@ -38,21 +38,21 @@ unsigned long acpi_fill_madt(unsigned long current)
 	device_t dev = 0;
     struct resource* res = NULL;
 
- 
+
 	// SJM: Hard-code CPU LAPIC entries for now
 	//		Use SourcePoint numbering of processors
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6);
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7);
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0);
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1);
-	
+
 
 	// Southbridge IOAPIC
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, 0xfec00000, irq_start);
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
 
 	// P64H2#2 Bus A IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -60,7 +60,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
 
 	// P64H2#2 Bus B IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -69,7 +69,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 
 	// P64H2#1 Bus A IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
 
 	// P64H2#1 Bus B IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -104,7 +104,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* Align ACPI tables to 16byte */
 	start   = ( start + 0x0f ) & -0x10;
 	current = start;
-	
+
 	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
@@ -115,10 +115,10 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	/* clear all table memory */
 	memset((void *)start, 0, current - start);
-	
+
 	acpi_write_rsdp(rsdp, rsdt, NULL);
 	acpi_write_rsdt(rsdt);
-	
+
 	/*
 	 * We explicitly add these tables later on:
 	 */
diff --git a/src/mainboard/intel/xe7501devkit/cmos.layout b/src/mainboard/intel/xe7501devkit/cmos.layout
index 494af5bb61..baae5eb617 100644
--- a/src/mainboard/intel/xe7501devkit/cmos.layout
+++ b/src/mainboard/intel/xe7501devkit/cmos.layout
@@ -1,4 +1,4 @@
-# NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails: 
+# NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails:
 # "Error - Name  is an invalid identifier in line"
 
 entries
diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h
index 30ae8e7a73..9ac2aee3f8 100644
--- a/src/mainboard/intel/xe7501devkit/ioapic.h
+++ b/src/mainboard/intel/xe7501devkit/ioapic.h
@@ -1,6 +1,6 @@
-// IOAPIC addresses determined by coreboot enumeration. 
+// IOAPIC addresses determined by coreboot enumeration.
 // Someday add functions to get APIC IDs and versions from the chips themselves.
-	
+
 #define IOAPIC_ICH3				2
 #define IOAPIC_P64H2_2_BUS_B	3	// IOAPIC 3 at 01:1c.0  MBAR = fe300000 DataAddr = fe300010
 #define IOAPIC_P64H2_2_BUS_A	4	// IOAPIC 4 at 01:1e.0  MBAR = fe301000 DataAddr = fe301010
diff --git a/src/mainboard/intel/xe7501devkit/irq_tables.c b/src/mainboard/intel/xe7501devkit/irq_tables.c
index b329351b6b..951b08f5f8 100644
--- a/src/mainboard/intel/xe7501devkit/irq_tables.c
+++ b/src/mainboard/intel/xe7501devkit/irq_tables.c
@@ -35,17 +35,17 @@ const struct irq_routing_table intel_irq_routing_table = {
 		// bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15
 		// ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13
 		// Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
-		
+
 		//											INTA#			   INTB#		     INTC#		      INTD#
 	//  bus,				device #  		   {link  , bitmap}, {link  , bitmap}, {link  , bitmap}, {link  , bitmap},  slot, rfu
-		
+
 		{PCI_BUS_CHIPSET,	PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// IDE / SMBus
 		{PCI_BUS_CHIPSET,	PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT},   0, 0},	// USB 1.1
-		
+
 		// P64H2#2 Bus A
 		{PCI_BUS_P64H2_2_A, PCI_DEVFN(1, 0),  {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// SCSI
 			// NOTE: Hotplug disabled on this bus
-		
+
 		// P64H2#2 Bus B
 		{PCI_BUS_P64H2_2_B, PCI_DEVFN(1, 0),  {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}},  23, 0},	// Slot 2A (J23)
 		{PCI_BUS_P64H2_2_B, PCI_DEVFN(2, 0),  {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}},  24, 0},	// Slot 2B (J24)
@@ -61,7 +61,7 @@ const struct irq_routing_table intel_irq_routing_table = {
 		{PCI_BUS_P64H2_1_B, PCI_DEVFN(1, 0),  {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// GB Ethernet
 		{PCI_BUS_P64H2_1_B, PCI_DEVFN(2, 0),  {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}},  21, 0},	// Slot 1B (J21)
 			// NOTE: Hotplug disabled on this bus
-	
+
 		// ICH-3 PCI bus
 		{PCI_BUS_ICH3,		PCI_DEVFN(0, 0),  {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// Video
 		{PCI_BUS_ICH3,		PCI_DEVFN(2, 0),  {{PIRQ_C, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_B, 0xdcf8}},  11, 0},	// Debug slot (J11)
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
index ee8299389d..2f48e83285 100644
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ b/src/mainboard/intel/xe7501devkit/mptable.c
@@ -40,14 +40,14 @@ static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
 	smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, 0xfec00000);	// APIC ID, Version, Address
 
 	// P64H2#2 Bus A IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base);
 
 	// P64H2#2 Bus B IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -55,14 +55,14 @@ static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
 
 
 	// P64H2#1 Bus A IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base);
 
 	// P64H2#1 Bus B IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -98,11 +98,11 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(4, INT_B), 	IOAPIC_P64H2_2_BUS_B,   13);	// Slot 2D (J12)
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(4, INT_C), 	IOAPIC_P64H2_2_BUS_B,   14);	// Slot 2D (J12)
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(4, INT_D), 	IOAPIC_P64H2_2_BUS_B,   15);	// Slot 2D (J12)
-	
+
 	// P64H2#2 Bus A
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_P64H2_2_A, 	PCI_IRQ(1, INT_A),	IOAPIC_P64H2_2_BUS_A,	 0);	// SCSI
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_P64H2_2_A, 	PCI_IRQ(1, INT_B),	IOAPIC_P64H2_2_BUS_A,	 1);	// SCSI
-	
+
 	// P64H2#1 Bus B
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_B, 	PCI_IRQ(1, INT_A), 	IOAPIC_P64H2_1_BUS_B,    0);	// GB Ethernet
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_B, 	PCI_IRQ(2, INT_A), 	IOAPIC_P64H2_1_BUS_B,    4);	// Slot 1B (J21)
@@ -117,13 +117,13 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_A, 	PCI_IRQ(1, INT_D), 	IOAPIC_P64H2_1_BUS_A,    3);	// Slot 1A (J20)
 
 	// ICH-3
-	
+
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(0, INT_A),	IOAPIC_ICH3,			16);	// Video
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(2, INT_A),	IOAPIC_ICH3,			18);	// Debug slot (J11)
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(2, INT_B),	IOAPIC_ICH3,			19);	// Debug slot (J11)
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(2, INT_C),	IOAPIC_ICH3,			16);	// Debug slot (J11)
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(2, INT_D),	IOAPIC_ICH3,			17);	// Debug slot (J11)
-	
+
 	// TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?
 
 	// Super I/O (ISA interrupts)
diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c
index 003a37f31c..99f00212c1 100644
--- a/src/mainboard/intel/xe7501devkit/romstage.c
+++ b/src/mainboard/intel/xe7501devkit/romstage.c
@@ -48,7 +48,7 @@ static void main(unsigned long bist)
 		},
 	};
 
-	if (bist == 0) 
+	if (bist == 0)
 	{
 		// Skip this if there was a built in self test failure
 		early_mtrr_init();
@@ -68,14 +68,14 @@ static void main(unsigned long bist)
 
 	// If this is a warm boot, some initialization can be skipped
 
-	if (!bios_reset_detected()) 
+	if (!bios_reset_detected())
 	{
 		enable_smbus();
 		// dump_spd_registers(&memctrl[0]);
 		// dump_smbus_registers();
 		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	}
-	
+
 	// NOTE: ROMCC dies with an internal compiler error
 	//		 if the following line is removed.
 	print_debug("SDRAM is up.\n");