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| author | Felix Singer <felix.singer@secunet.com> | 2020-08-04 16:47:10 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-08-07 20:35:29 +0000 |
| commit | 3de90d134494203556a81c47a6640ae101674114 (patch) | |
| tree | 85ec6d856aeba4da218ea3ae5038565eab6bbd89 /src/mainboard/intel | |
| parent | b7594b09b597075b3072e12c8338ca0cee66c006 (diff) | |
| download | coreboot-3de90d134494203556a81c47a6640ae101674114.tar.xz | |
soc/intel/cnl: Set Heci1Disable depending on devicetree config
Currently HECI1 gets enabled by the option HeciEnabled, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement/disablement of the HECI1 device.
All corresponding mainboards were checked if the devicetree matches
the HeciEnabled setting, and adjusted where necessary.
Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 01d970ca56..0b40a5c359 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -8,9 +8,6 @@ chip soc/intel/cannonlake register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" - # HECI - register "HeciEnabled" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" |