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authorVladimir Serbinenko <phcoder@gmail.com>2014-02-05 19:46:45 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2014-02-25 00:57:35 +0100
commit4337020b950454815204eed4e43a894be0b125ca (patch)
tree7aa3a4ad420a54b3079f3216d577aafab1bca2e0 /src/mainboard/intel
parent20f83d56561879045ecade24d51e79dfb151baf6 (diff)
downloadcoreboot-4337020b950454815204eed4e43a894be0b125ca.tar.xz
Remove CACHE_ROM.
With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs depending on system configuration, hence screwing up I/O access and cache coherency in worst cases. CACHE_ROM requires the user to sanity check their boot output because the feature is brittle. The working configuration is dependent on I/O hole size, ram size, and chipset. Because of this the current implementation can leave a system configured in an inconsistent state leading to unexpected results such as poor performance and/or inconsistent cache-coherency Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5146 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/wtm2/Kconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig
index 8e13108af3..00ea604bb8 100644
--- a/src/mainboard/intel/wtm2/Kconfig
+++ b/src/mainboard/intel/wtm2/Kconfig
@@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
- select CACHE_ROM
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MONOTONIC_TIMER_MSR