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| author | Sven Schnelle <svens@stackframe.org> | 2011-02-21 09:39:17 +0000 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2011-02-21 09:39:17 +0000 |
| commit | 541269bc85b7d63b7660cd299e70335a52d5fdf4 (patch) | |
| tree | 5494ba16137a9830a8a5a9bb3ccd5c856f7962e6 /src/mainboard/intel | |
| parent | 0c8e664713d4dc726bedb5ba0b2e356eed9ae14c (diff) | |
| download | coreboot-541269bc85b7d63b7660cd299e70335a52d5fdf4.tar.xz | |
[i945] Add SPD adress mapping
The current code works only with dual channel if Channel 0 uses SPD address
0x50/0x51, while the second channel has to use 0x52/0x53.
For hardware that uses other addresses (like the ThinkPad X60) this means we
get only one module running instead of both.
This patch adds a second parameter to sdram_initialize, which is an array with
2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single
DIMM socket. If NULL is given as the second parameter, the code uses the old
addressing scheme.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/d945gclf/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index f7056737dc..6dfc1444bd 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -243,7 +243,7 @@ void main(unsigned long bist) dump_spd_registers(); #endif - sdram_initialize(boot_mode); + sdram_initialize(boot_mode, NULL); /* Perform some initialization that must run before stage2 */ early_ich7_init(); |