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| author | Furquan Shaikh <furquan@google.com> | 2020-11-30 15:41:51 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-12-08 22:58:31 +0000 |
| commit | 68ca21ae3dfb4d22b15b0be8b6e337eb9949471a (patch) | |
| tree | 2c39238b92c5a06bd51dc01648a58cf9bdd06e91 /src/mainboard/intel | |
| parent | 28e1d0ea551cd37cacbfe7d080345daa6fb3ad91 (diff) | |
| download | coreboot-68ca21ae3dfb4d22b15b0be8b6e337eb9949471a.tar.xz | |
mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB
This change restricts SI_ME region to live below the 16MiB boundary to
ensure that no regions cross the 16MiB boundary as the extended BIOS
window checker for FMAP complains about it.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/tglrvp/chromeos.fmd | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd index bfbd304d36..1e2e7920cf 100644 --- a/src/mainboard/intel/tglrvp/chromeos.fmd +++ b/src/mainboard/intel/tglrvp/chromeos.fmd @@ -1,8 +1,8 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1081000 { + SI_ALL@0x0 0x1000000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x1000000 + SI_ME@0x81000 } SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { |