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| author | Hannah Williams <hannah.williams@intel.com> | 2016-03-28 15:11:46 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-26 17:25:13 +0200 |
| commit | 988b3fd2ee3f761340d43a09af12d2b66f841b5a (patch) | |
| tree | 43d5e9087e9db48f5b30e3f58a008fbfc72f6396 /src/mainboard/intel | |
| parent | 483004f6d78767cf97c383d491e5ddc43818256f (diff) | |
| download | coreboot-988b3fd2ee3f761340d43a09af12d2b66f841b5a.tar.xz | |
mainboard/intel/amenia: Disable Integrated Sensor Hub
Providing an option to enable or disable ISH interface. Leaving it
disabled for now.
Change-Id: Id4e71d60a6c2da6c6c070d41f66f6c161de38595
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14895
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/amenia/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 38a2de2c43..af06848a84 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -7,6 +7,9 @@ chip soc/intel/apollolake register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "0" # SSD + # Integrated Sensor Hub + register "integrated_sensor_hub_enable" = "0" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF |