summaryrefslogtreecommitdiff
path: root/src/mainboard/intel
diff options
context:
space:
mode:
authorJoel Kitching <kitching@google.com>2019-04-07 00:37:14 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-04-11 11:23:26 +0000
commitae0fb762a2b0592a9734120bd14e0b7a98af9d31 (patch)
tree48bff02725b52be3e38e4adb7584ab204c0d7020 /src/mainboard/intel
parent482eec0e1bb43aee59cdbb4ec39068fecbcc012b (diff)
downloadcoreboot-ae0fb762a2b0592a9734120bd14e0b7a98af9d31.tar.xz
chromeos: clean up "recovery" and "write protect" GPIOs
The "write protect" GPIO's cached value is never actually read after entering depthcharge. Ensure the value from get_write_protect_state() is being transferred accurately, so that we may read this GPIO value in depthcharge without resampling. The cached value of the "recovery" GPIO is read only on certain boards which have a physical recovery switch. Correct some of the values sent to boards which presumably never read the previously incorrect value. Most of these inaccuracies are from non-inverted values on ACTIVE_LOW GPIOs. BUG=b:124141368, b:124192753, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/baskingridge/chromeos.c2
-rw-r--r--src/mainboard/intel/emeraldlake2/chromeos.c4
-rw-r--r--src/mainboard/intel/wtm2/chromeos.c4
3 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index 0c8d0b22ab..f1fd3ed84c 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -30,7 +30,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
/* Write Protect: GPIO22 */
- {0, ACTIVE_LOW, get_write_protect_state(), "write protect"},
+ {0, ACTIVE_LOW, !get_write_protect_state(), "write protect"},
/* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */
{69, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index aa0d9aad1b..78610d398d 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -30,10 +30,10 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
/* Write Protect: GPIO48 */
- {48, ACTIVE_LOW, get_write_protect_state(), "write protect"},
+ {48, ACTIVE_LOW, !get_write_protect_state(), "write protect"},
/* Recovery: GPIO22 */
- {22, ACTIVE_LOW, get_recovery_mode_switch(), "recovery"},
+ {22, ACTIVE_LOW, !get_recovery_mode_switch(), "recovery"},
/* Hard code the lid switch GPIO to open. */
{-1, ACTIVE_HIGH, 1, "lid"},
diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c
index 6464ef4c0f..0f5cfbba35 100644
--- a/src/mainboard/intel/wtm2/chromeos.c
+++ b/src/mainboard/intel/wtm2/chromeos.c
@@ -28,8 +28,8 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
- {-1, ACTIVE_HIGH, 0, "write protect"},
- {-1, ACTIVE_HIGH, REC_MODE_SETTING, "recovery"},
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{-1, ACTIVE_HIGH, 1, "lid"}, // force open
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},