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authorPatrick Georgi <patrick.georgi@coresystems.de>2009-08-11 17:35:02 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2009-08-11 17:35:02 +0000
commitb339e10f04869a3d8da31e7d52831c32c57302a2 (patch)
tree9876043ec4255e1dcf619890eba579872273564f /src/mainboard/intel
parent401c8d1da2a5292649498ec3a2c8414bd8ecd62c (diff)
downloadcoreboot-b339e10f04869a3d8da31e7d52831c32c57302a2.tar.xz
Enable CBFS everywhere. All boards compiled for me (abuild tested),
and we will fix issues as they appear. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/jarrell/Config.lb2
-rw-r--r--src/mainboard/intel/jarrell/Options.lb4
-rw-r--r--src/mainboard/intel/mtarvon/Config.lb2
-rw-r--r--src/mainboard/intel/mtarvon/Options.lb4
-rw-r--r--src/mainboard/intel/truxton/Config.lb2
-rw-r--r--src/mainboard/intel/truxton/Options.lb4
-rw-r--r--src/mainboard/intel/xe7501devkit/Config.lb2
-rw-r--r--src/mainboard/intel/xe7501devkit/Options.lb4
8 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb
index 01bcf82862..4fbd3fb22c 100644
--- a/src/mainboard/intel/jarrell/Config.lb
+++ b/src/mainboard/intel/jarrell/Config.lb
@@ -4,7 +4,7 @@
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
diff --git a/src/mainboard/intel/jarrell/Options.lb b/src/mainboard/intel/jarrell/Options.lb
index 665b7d0931..aac7a38d0a 100644
--- a/src/mainboard/intel/jarrell/Options.lb
+++ b/src/mainboard/intel/jarrell/Options.lb
@@ -161,7 +161,7 @@ default CONFIG_HEAP_SIZE=0x8000
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
-default CONFIG_FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
##
## Coreboot C code runs at this location in RAM
@@ -246,5 +246,5 @@ default CONFIG_CONSOLE_BTEXT=0
# CBFS
#
#
-default CONFIG_CBFS=0
+default CONFIG_CBFS=1
end
diff --git a/src/mainboard/intel/mtarvon/Config.lb b/src/mainboard/intel/mtarvon/Config.lb
index 0613d7d369..e5e598214d 100644
--- a/src/mainboard/intel/mtarvon/Config.lb
+++ b/src/mainboard/intel/mtarvon/Config.lb
@@ -18,7 +18,7 @@
##
## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
diff --git a/src/mainboard/intel/mtarvon/Options.lb b/src/mainboard/intel/mtarvon/Options.lb
index 17ccf4bc64..c5f2782fd9 100644
--- a/src/mainboard/intel/mtarvon/Options.lb
+++ b/src/mainboard/intel/mtarvon/Options.lb
@@ -150,7 +150,7 @@ default CONFIG_HEAP_SIZE=0x8000
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
-default CONFIG_FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
##
## coreboot C code runs at this location in RAM
@@ -229,5 +229,5 @@ default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
# CBFS
#
#
-default CONFIG_CBFS=0
+default CONFIG_CBFS=1
end
diff --git a/src/mainboard/intel/truxton/Config.lb b/src/mainboard/intel/truxton/Config.lb
index 4a80852317..7ec2da81b6 100644
--- a/src/mainboard/intel/truxton/Config.lb
+++ b/src/mainboard/intel/truxton/Config.lb
@@ -18,7 +18,7 @@
##
## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
diff --git a/src/mainboard/intel/truxton/Options.lb b/src/mainboard/intel/truxton/Options.lb
index 0c8fc291ec..2f98066cd3 100644
--- a/src/mainboard/intel/truxton/Options.lb
+++ b/src/mainboard/intel/truxton/Options.lb
@@ -150,7 +150,7 @@ default CONFIG_HEAP_SIZE=0x8000
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
-default CONFIG_FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
##
## coreboot C code runs at this location in RAM
@@ -231,5 +231,5 @@ default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
# CBFS
#
#
-default CONFIG_CBFS=0
+default CONFIG_CBFS=1
end
diff --git a/src/mainboard/intel/xe7501devkit/Config.lb b/src/mainboard/intel/xe7501devkit/Config.lb
index 2ac608f066..4557a6a6d5 100644
--- a/src/mainboard/intel/xe7501devkit/Config.lb
+++ b/src/mainboard/intel/xe7501devkit/Config.lb
@@ -1,5 +1,5 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
diff --git a/src/mainboard/intel/xe7501devkit/Options.lb b/src/mainboard/intel/xe7501devkit/Options.lb
index 20289a2ee3..325edba261 100644
--- a/src/mainboard/intel/xe7501devkit/Options.lb
+++ b/src/mainboard/intel/xe7501devkit/Options.lb
@@ -79,7 +79,7 @@ default CONFIG_ROM_IMAGE_SIZE = 65536
## Build code for the fallback boot?
##
default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
## Delay timer options
@@ -244,5 +244,5 @@ default CONFIG_DEBUG=1
# CBFS
#
#
-default CONFIG_CBFS=0
+default CONFIG_CBFS=1
end