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authorArthur Heymans <arthur@aheymans.xyz>2019-11-09 14:29:04 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-12 18:23:07 +0000
commitc484da1a98610d783131a3a3998c0a999b97f9f5 (patch)
treec4e25f9b4fbde15a9962b9d0c7d7117997e26ad1 /src/mainboard/intel
parentfecf77770b8e68b9ef82021ca53c31db93736d93 (diff)
downloadcoreboot-c484da1a98610d783131a3a3998c0a999b97f9f5.tar.xz
sb/intel/i82801jx: Add common code for LPC decode
Change-Id: Id706da33f06ceeec39ea50301130770226f0474e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/dg43gt/devicetree.cb3
-rw-r--r--src/mainboard/intel/dg43gt/romstage.c15
2 files changed, 4 insertions, 14 deletions
diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb
index be0b911a5a..38ae29b031 100644
--- a/src/mainboard/intel/dg43gt/devicetree.cb
+++ b/src/mainboard/intel/dg43gt/devicetree.cb
@@ -42,6 +42,9 @@ chip northbridge/intel/x4x # Northbridge
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0xb"
+ register "gen1_dec" = "0x00fc0601"
+ register "gen2_dec" = "0x00fc0291"
+
device pci 19.0 on end # GBE
device pci 1a.0 on end # USB
device pci 1a.1 on end # USB
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
index 018df1bedf..6e645b5630 100644
--- a/src/mainboard/intel/dg43gt/romstage.c
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -53,19 +53,6 @@ static void mb_gpio_init(void)
RCBA32(0x3f00) = 0x0000000b;
}
-static void ich10_enable_lpc(void)
-{
- /* Configure serial IRQs.*/
- pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
- pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
- | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
- | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
- | COMB_LPC_EN | COMA_LPC_EN);
- pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0xfc0601);
- pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xfc0291);
- pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0);
-}
-
void mainboard_romstage_entry(void)
{
const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
@@ -73,7 +60,7 @@ void mainboard_romstage_entry(void)
u8 s3_resume;
/* Set southbridge and Super I/O GPIOs. */
- ich10_enable_lpc();
+ i82801jx_lpc_setup();
mb_gpio_init();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);