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authorArthur Heymans <arthur@aheymans.xyz>2017-09-22 12:22:24 +0200
committerFelix Held <felix-coreboot@felixheld.de>2018-05-01 17:42:30 +0000
commit16a70a48c68f9027b0900e15fc9e3bc14391ad44 (patch)
tree70409c259f50e463913d068a00d1e0f600f8a578 /src/mainboard/intel
parentdfce932cf0c3d13f41892d6e40d56fbaa8e16240 (diff)
downloadcoreboot-16a70a48c68f9027b0900e15fc9e3bc14391ad44.tar.xz
nb/intel/x4x: Change memory layout to improve MTRR
This change also makes sure that the sum the uma regions (TSEG, GSM, GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between 2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR setup for ramstage. At least tianocore requires this and fails to boot without it. Better MTRR are achieved by making the memory 'hole' till 4GiB exactly 2Gib. This code mimics how it is done in nb/intel/gm45 and achieves similar results. TSEG is enabled and set to 8M since this makes it easier to reuse the common smm setup / parallel mp code and makes it possible to cache the ramstage in there like how it's done on newer targets. TESTED on Intel DG43GT. Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/dg43gt/cmos.layout1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout
index 1175cafdc2..abeff71f8b 100644
--- a/src/mainboard/intel/dg43gt/cmos.layout
+++ b/src/mainboard/intel/dg43gt/cmos.layout
@@ -92,7 +92,6 @@ enumerations
7 2 Keep
10 0 AHCI
10 1 Compatible
-11 0 1M
11 1 4M
11 2 8M
11 3 16M