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authorDuncan Laurie <dlaurie@chromium.org>2013-05-01 11:30:24 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-11-25 23:11:46 +0100
commit1d048ca56080488b525077c99f94cf478efa43ed (patch)
treec96036babc9c9d790182fd7b6927933db614de08 /src/mainboard/intel
parent144f7b29ad995da897ec6c6ee4f87bed2ec7d28e (diff)
downloadcoreboot-1d048ca56080488b525077c99f94cf478efa43ed.tar.xz
lynxpoint: Move ME lock down to ramstage
Now that we have RW ramstage we don't need to have the management engine lock down step done in a final SMM. ME: mkhi_end_of_post ME: END OF POST message successful (0) PCI: 00:16.0: Disabling device Change-Id: I9db4e72e38be58cc875c1622a966d8fcacc83280 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49757 Reviewed-on: http://review.coreboot.org/4153 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/baskingridge/mainboard_smi.c1
-rw-r--r--src/mainboard/intel/wtm2/mainboard_smi.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c
index e543494b25..f24af67579 100644
--- a/src/mainboard/intel/baskingridge/mainboard_smi.c
+++ b/src/mainboard/intel/baskingridge/mainboard_smi.c
@@ -84,7 +84,6 @@ int mainboard_smi_apmc(u8 apmc)
return 0;
}
- intel_me_finalize_smm();
intel_pch_finalize_smm();
intel_northbridge_haswell_finalize_smm();
intel_cpu_haswell_finalize_smm();
diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c
index 3ffc68441d..bcc94d6f2b 100644
--- a/src/mainboard/intel/wtm2/mainboard_smi.c
+++ b/src/mainboard/intel/wtm2/mainboard_smi.c
@@ -60,7 +60,6 @@ int mainboard_smi_apmc(u8 apmc)
return 0;
}
- intel_me_finalize_smm();
intel_pch_finalize_smm();
intel_northbridge_haswell_finalize_smm();
intel_cpu_haswell_finalize_smm();