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authorDamien Zammit <damien@zamaudio.com>2016-01-26 14:03:37 +1100
committerMartin Roth <martinroth@google.com>2016-01-28 17:57:25 +0100
commit63eb9172758c7ed9f14713ab71a0281125ef8a28 (patch)
treedb4af5fe897b99f42aa9004f2b90ba635e483210 /src/mainboard/intel
parent761c2942ef1a26dde2b1c9a126c62f091daef789 (diff)
downloadcoreboot-63eb9172758c7ed9f14713ab71a0281125ef8a28.tar.xz
mb/intel/d510mo: Use SATA AHCI by default
Change-Id: I6f9772c5bcf9a50dfbc3d1cfaeb79f4454d1fb27 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13454 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/d510mo/devicetree.cb6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb
index df5a0f9bda..c0f38de9dd 100644
--- a/src/mainboard/intel/d510mo/devicetree.cb
+++ b/src/mainboard/intel/d510mo/devicetree.cb
@@ -38,10 +38,8 @@ chip northbridge/intel/pineview # Northbridge
register "pirqf_routing" = "0x0b"
register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b"
- register "ide_legacy_combined" = "0x1"
- register "ide_enable_primary" = "0x1"
- register "ide_enable_secondary" = "0x0"
- register "sata_ahci" = "0x0"
+ register "sata_ahci" = "0x1"
+ register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x20000040"
device pci 1b.0 on end # Audio