diff options
| author | Nico Huber <nico.h@gmx.de> | 2019-11-17 02:34:53 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:51:57 +0000 |
| commit | 6760e0bdcd37e904c121800652cd2ac3920d9cd9 (patch) | |
| tree | 576cc3efed90173d7093f4f93878a42d0bbe363f /src/mainboard/intel | |
| parent | 1d29b7bbceed82a2161e249474086169ac3039f4 (diff) | |
| download | coreboot-6760e0bdcd37e904c121800652cd2ac3920d9cd9.tar.xz | |
sb/intel/bd82x6x: Handle enabling of GbE
The integrated GbE port is toggled via the Backed-Up Control (BUC)
register. We already disable it according to the devicetree setting
but never enabled it. This could lead to the confusing situation
that it was disabled before (different build, vendor BIOS, etc.)
but shouldn't be anymore.
As we need a full reset after enabling GbE, do it in early PCH init.
Change-Id: I9db3d1923684b938d2c9f5b369b0953570c7fc15
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/dcp847ske/early_southbridge.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 1f76db8e52..34310a0094 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -33,16 +33,6 @@ void mainboard_late_rcba_config(void) /* Disable devices */ RCBA32(FD) |= PCH_DISABLE_P2P; -#if CONFIG(USE_NATIVE_RAMINIT) - /* Enable Gigabit Ethernet */ - if (RCBA32(BUC) & PCH_DISABLE_GBE) { - RCBA32(BUC) &= ~PCH_DISABLE_GBE; - /* Datasheet says clearing the bit requires a reset after */ - printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n"); - full_reset(); - } -#endif - /* Set "mobile" bit in MCH (which makes sense layout-wise). */ /* Note sure if this has any effect at all though. */ MCHBAR32(0x0004) |= 0x00001000; |