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| author | Rudolf Marek <r.marek@assembler.cz> | 2013-05-04 00:08:34 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-09-19 19:53:30 +0200 |
| commit | 8f485dee0d38c1c5f1a29fa8840602774ef5f63d (patch) | |
| tree | e0d147305a165652ab3582dcbbf29de8578b39fa /src/mainboard/intel | |
| parent | ad690f2e8182b182b4c343d2238bb079e6bb8db2 (diff) | |
| download | coreboot-8f485dee0d38c1c5f1a29fa8840602774ef5f63d.tar.xz | |
ASUS F2A85-M: Correct and clean up PCIe config
Assign the lanes correctly to the physical slots
on the motherboard in `PlatformGnbPcie.c`.
• UMI is connected to SB via 4x PCIe bridge 8.
• The blue x16 slot is not shared with DDI and is routed
through PCIe bridge 2.
• The black x8 slot is in fact a x4 slot and uses all 4 GPPs
from the CPU.
• Assume that DDI is on out-of-PCIe-band lanes.
Change-Id: I44c4c83e6a8e31d6150a602a0993972ac63105bd
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3194
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Diffstat (limited to 'src/mainboard/intel')
0 files changed, 0 insertions, 0 deletions