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authorArthur Heymans <arthur@aheymans.xyz>2017-09-07 18:15:28 +0200
committerArthur Heymans <arthur@aheymans.xyz>2017-09-12 22:25:13 +0000
commit92ce1fb45eda81d8667db63ec8eb649ed87c743c (patch)
treec600fcd8d94a6eced464432d5b146d170d4baecd /src/mainboard/intel
parent91d98e78ff8115deecc8ec01c4f788bf29461233 (diff)
downloadcoreboot-92ce1fb45eda81d8667db63ec8eb649ed87c743c.tar.xz
mb/intel/dg43gt: Fix smbus IRQ
This board uses the reset defaults for DxxIP and DxxIR. The datasheet "Intel ® I/O Controller Hub 10 (ICH10) Family" mistakenly says in the D31IP register that all function have INTB as default. This is however not true as documented in the reset default value. This fixes the DSDT such that the SMBus device gets a route for the INT C interrupt it uses. Change-Id: I3dd1308fb7acec86b90ecd9d2079cf9a58702c40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21442 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl b/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl
index 510af9abb6..8e56679f40 100644
--- a/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl
+++ b/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl
@@ -52,6 +52,8 @@ Method(_PRT)
Package() { 0x001dffff, 3, 0, 0x13 },
/* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */
Package() { 0x001fffff, 1, 0, 0x11 },
+ Package() { 0x001fffff, 2, 0, 0x12 },
+ Package() { 0x001fffff, 3, 0, 0x13 },
})
} Else {
Return (Package() {
@@ -86,6 +88,8 @@ Method(_PRT)
Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
/* PATA/SATA/SMBUS 0:1f.1-3 */
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
})
}
}