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authorDuncan Laurie <dlaurie@google.com>2018-11-08 15:46:16 -0700
committerDuncan Laurie <dlaurie@chromium.org>2018-11-13 16:32:27 +0000
commit98456f4ee6e1d7df2863e2fafe8e505522a48da8 (patch)
tree3631482088033a55286946fa7cbbb17d4479b50f /src/mainboard/intel
parent6efa5c38460b28d650231429ae4fc9a0be7fddba (diff)
downloadcoreboot-98456f4ee6e1d7df2863e2fafe8e505522a48da8.tar.xz
mb/cannonlake: Remove SmbusEnable from devicetree
Remove the SmbusEnable parameter from all Cannon Lake mainboards. Instead this will be determined by the enable state of the SMBUS PCI device. Change-Id: I7ece6768da4c517747af12a07012583575816ae1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb1
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb1
-rw-r--r--src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb1
-rw-r--r--src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb1
-rw-r--r--src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb1
5 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index da439d5473..bb963c9523 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -6,7 +6,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
- register "SmbusEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index a1c85865f6..55afde2cae 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -6,7 +6,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
- register "SmbusEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
index 4a2fad9540..35aa624481 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
@@ -7,7 +7,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "RMT" = "1"
- register "SmbusEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb
index 2b47f00d51..bbfc9e7913 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb
@@ -7,7 +7,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "RMT" = "1"
- register "SmbusEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb
index da439d5473..bb963c9523 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb
@@ -6,7 +6,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
- register "SmbusEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"