diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-09-05 03:37:44 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-10-16 14:18:04 +0200 |
| commit | c845b43f0a404adaf96808a122c591c5552dc818 (patch) | |
| tree | 4ee8868a9208a1504adb8453be70af0ccaf47156 /src/mainboard/intel | |
| parent | dca2c468fc4eaba3a6123eb3ab97463db0254650 (diff) | |
| download | coreboot-c845b43f0a404adaf96808a122c591c5552dc818.tar.xz | |
sandybridge: Move common northbridge finalize to northbridge code.
Change-Id: I6d4178e5aaffc1330b0953b0601bf6b448250a8e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6920
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/romstage.c | 24 |
1 files changed, 3 insertions, 21 deletions
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index e10e7b62a3..c9c2b1d41f 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -297,35 +297,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); |