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authorLee Leahy <leroy.p.leahy@intel.com>2016-09-28 14:10:06 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2016-09-30 01:15:44 +0200
commite1654235fd941b4a4cfb5f75325fe0a496a24c5f (patch)
tree1538f3c4ef350dc03d4fe323bcb5b94ac5c2df33 /src/mainboard/intel
parent127b5d1270fc3c7ea8be7c80670be8dcd9ea4147 (diff)
downloadcoreboot-e1654235fd941b4a4cfb5f75325fe0a496a24c5f.tar.xz
mainboard/intel/quark: Add FSP selection values
Add Kconfig values to select the FSP setup: * FSP version: 1.1 or 2.0 * Implementation: Subroutine or SEC/PEI core based * Build type: DEBUG or RELEASE * Enable all debugging for FSP * Remove USE_FSP1_1 and USE_FSP2_0 Look for include files in vendorcode/intel/fsp/fsp???/quark BRANCH=none BUG=None TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2 Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16806 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/galileo/Kconfig108
-rw-r--r--src/mainboard/intel/galileo/Makefile.inc4
2 files changed, 101 insertions, 11 deletions
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
index 2acc439746..0c1fe5b9c5 100644
--- a/src/mainboard/intel/galileo/Kconfig
+++ b/src/mainboard/intel/galileo/Kconfig
@@ -18,11 +18,10 @@ if BOARD_INTEL_GALILEO
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
- select CREATE_BOARD_CHECKLIST
+# select CREATE_BOARD_CHECKLIST
select ENABLE_BUILTIN_HSUART1
select HAVE_ACPI_TABLES
select SOC_INTEL_QUARK
- select USE_FSP1_1
config MAINBOARD_DIR
string
@@ -45,16 +44,107 @@ config GALILEO_GEN2
runtime. Select which generation of the Galileo that coreboot
should initialize.
-config USE_FSP1_1
- bool
- default n
+choice
+ prompt "FSP version"
+ default FSP_VERSION_1_1
+
+config FSP_VERSION_1_1
+ bool "FSP 1.1"
+ select CREATE_BOARD_CHECKLIST
select PLATFORM_USES_FSP1_1
# select ADD_FSP_RAW_BIN
-
-config USE_FSP2_0
- bool
- default n
+ help
+ Use FSP 1_1 binary
+config FSP_VERSION_2_0
+ bool "FSP 2.0"
select PLATFORM_USES_FSP2_0
select POSTCAR_STAGE
+ help
+ Use FSP 2.0 binary
+
+endchoice
+
+config FSP_VERSION
+ string
+ default "fsp1_1" if FSP_VERSION_1_1
+ default "fsp2_0" if FSP_VERSION_2_0
+
+choice
+ prompt "FSP binary type"
+ default FSP_BUILD_TYPE_DEBUG
+
+config FSP_BUILD_TYPE_DEBUG
+ bool "Debug"
+ help
+ Use the debug version of FSP
+config FSP_BUILD_TYPE_RELEASE
+ bool "Release"
+ help
+ Use the release version of FSP
+
+endchoice
+
+config FSP_BUILD_TYPE
+ string
+ default "DEBUG" if FSP_BUILD_TYPE_DEBUG
+ default "RELEASE" if FSP_BUILD_TYPE_RELEASE
+
+choice
+ prompt "FSP type"
+ depends on FSP_VERSION_2_0 || FSP_VERSION_1_1
+ default FSP_TYPE_1_1_PEI if FSP_VERSION_1_1
+ default FSP_TYPE_2_0_PEI if FSP_VERSION_2_0
+
+config FSP_TYPE_1_1
+ bool "MemInit subroutine"
+ depends on FSP_VERSION_1_1
+ help
+ FSP 1.1 implemented as subroutines, no EDK-II cores
+config FSP_TYPE_1_1_PEI
+ bool "SEC + PEI Core + MemInit PEIM"
+ depends on FSP_VERSION_1_1
+ help
+ FSP 1.1 implemented using SEC and PEI core
+config FSP_TYPE_2_0
+ bool "MemInit subroutine"
+ depends on FSP_VERSION_2_0
+ help
+ FSP 2.0 implemented as subroutines, no EDK-II cores
+config FSP_TYPE_2_0_PEI
+ bool "SEC + PEI Core + MemInit PEIM"
+ depends on FSP_VERSION_2_0
+ help
+ FSP 2.0 implemented using SEC and PEI core
+
+endchoice
+
+config FSP_TYPE
+ string
+ default "Fsp1_1" if FSP_TYPE_1_1
+ default "Fsp1_1Pei" if FSP_TYPE_1_1_PEI
+ default "Fsp2_0" if FSP_TYPE_2_0
+ default "Fsp2_0Pei" if FSP_TYPE_2_0_PEI
+
+config FSP_DEBUG_ALL
+ bool "Enable all FSP debug support"
+ depends on FSP_VERSION_2_0 || FSP_VERSION_1_1
+ default y
+# Enable display and verification for coreboot build tests
+ select BOOTBLOCK_CONSOLE
+ select DISPLAY_HOBS
+ select DISPLAY_MTRRS
+ select DISPLAY_SMM_MEMORY_MAP
+ select DISPLAY_UPD_DATA
+ select DISPLAY_ESRAM_LAYOUT if FSP_VERSION_2_0
+ select DISPLAY_FSP_CALLS_AND_STATUS if FSP_VERSION_2_0
+ select DISPLAY_FSP_HEADER if FSP_VERSION_2_0
+ select POSTCAR_CONSOLE if FSP_VERSION_2_0
+ select VERIFY_HOBS if FSP_VERSION_2_0
+ select DISPLAY_FSP_ENTRY_POINTS if FSP_VERSION_1_1
+ help
+ Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA
+ also turn on FSP 2.0 debug support for ESRAM_LAYOUT,
+ FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS
+ or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS
endif # BOARD_INTEL_QUARK
diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc
index efaf007677..16b2b4ac99 100644
--- a/src/mainboard/intel/galileo/Makefile.inc
+++ b/src/mainboard/intel/galileo/Makefile.inc
@@ -13,8 +13,8 @@
## GNU General Public License for more details.
##
-ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark
+ifeq ($(CONFIG_PLATFORM_USES_FSP2_0)$(CONFIG_PLATFORM_USES_FSP1_1),y)
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/$(CONFIG_FSP_VERSION)/quark
endif
bootblock-y += gpio.c