intel/kblrvp: Update mainboard configuration

Update devicetree.cb as per RVP3 mainboard.

* Enable & configure PCIE ports,
* Enable & configure USB ports,
* Enable SSIC for WWAN,
* Disable unused I2C ports,
* Disable deep S5,
* Disable HDA,
* Update VR config,

Updated gpio.h to disable pull down for SoC power button.

Change-Id: I235a1d44dabef16ded2aaad13aef36ca57f37c8e
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17247
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2 files changed, 60 insertions, 118 deletions

diff --git a/src/mainboard/intel/kblrvp/devicetree.cb b/src/mainboard/intel/kblrvp/devicetree.cb
index 8dded98470..104a454963 100644
--- a/src/mainboard/intel/kblrvp/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/devicetree.cb
@@ -1,14 +1,14 @@
 chip soc/intel/skylake
 
 	# Enable deep Sx states
-	register "deep_s5_enable" = "1"
+	register "deep_s5_enable" = "0"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
 
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE
 	# offset bits also need to be changed.
-	register "gpe0_dw0" = "GPP_B"
+	register "gpe0_dw0" = "GPP_C"
 	register "gpe0_dw1" = "GPP_D"
 	register "gpe0_dw2" = "GPP_E"
 
@@ -23,9 +23,6 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# FSP Configuration
-	register "EnableAzalia" = "1"
-	register "DspEnable" = "1"
-	register "IoBufferOwnership" = "3"
 	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
@@ -67,7 +64,7 @@ chip soc/intel/skylake
 	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
 	#+----------------+-------+-------+-------------+-------------+-------+
 	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
+	#| Psi2Threshold  | 5A    | 5A    | 5A          | 5A          | 5A    |
 	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
 	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
 	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
@@ -79,7 +76,7 @@ chip soc/intel/skylake
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1, \
 		.psi1threshold = 0x50, \
-		.psi2threshold = 0x10, \
+		.psi2threshold = 0x14, \
 		.psi3threshold = 0x4, \
 		.psi3enable = 1, \
 		.psi4enable = 1, \
@@ -142,29 +139,56 @@ chip soc/intel/skylake
 
 	register "FspSkipMpInit" = "1"
 
-	# Enable Root port 1 and 5.
+	# Enable Root ports.
+	# PCIE Port 1 x4 -> SLOT1
 	register "PcieRpEnable[0]" = "1"
-	register "PcieRpEnable[4]" = "1"
-	# Enable CLKREQ#
 	register "PcieRpClkReqSupport[0]" = "1"
+	register "PcieRpClkReqNumber[0]" = "2"
+
+	# PCIE Port 5 x1 -> SLOT2/LAN
+	register "PcieRpEnable[4]" = "1"
 	register "PcieRpClkReqSupport[4]" = "1"
-	# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
-	register "PcieRpClkReqNumber[0]" = "1"
-	register "PcieRpClkReqNumber[4]" = "2"
+	register "PcieRpClkReqNumber[4]" = "3"
+
+	# PCIE Port 6 x1 -> SLOT3
+	register "PcieRpEnable[5]" = "1"
+	register "PcieRpClkReqSupport[5]" = "1"
+	register "PcieRpClkReqNumber[5]" = "1"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C"  # Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C"  # Type-C Port 2
-	register "usb2_ports[2]" = "USB2_PORT_MID"     # Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MID"     # Type-A Port (card)
-	register "usb2_ports[6]" = "USB2_PORT_FLEX"    # Camera
-	register "usb2_ports[8]" = "USB2_PORT_LONG"    # Type-A Port (board)
+	# PCIE Port 7 Disabled
+	# PCIE Port 8 Disabled
+	# PCIE Port 9 x1 -> WLAN
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpClkReqSupport[8]" = "1"
+	register "PcieRpClkReqNumber[8]" = "5"
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
+	# PCIE Port 10 x1 -> WiGig
+	register "PcieRpEnable[9]" = "1"
+	register "PcieRpClkReqSupport[9]" = "1"
+	register "PcieRpClkReqNumber[9]" = "4"
 
-	register "i2c[4].voltage" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V
+	# USB 2.0 Enable all ports
+	register "usb2_ports[0]" = "USB2_PORT_MAX"	# TYPE-A Port
+	register "usb2_ports[1]" = "USB2_PORT_MAX"	# TYPE-A Port
+	register "usb2_ports[2]" = "USB2_PORT_MAX"	# Bluetooth
+	register "usb2_ports[4]" = "USB2_PORT_MAX"	# Type-A Port
+	register "usb2_ports[5]" = "USB2_PORT_MAX"	# TYPE-A Port
+	register "usb2_ports[6]" = "USB2_PORT_MAX"	# TYPE-A Port
+	register "usb2_ports[7]" = "USB2_PORT_MAX"	# TYPE-A Port
+	register "usb2_ports[8]" = "USB2_PORT_MAX"	# TYPE-A Port
+	register "usb2_ports[9]" = "USB2_PORT_MAX"	# TYPE-A Port
+	register "usb2_ports[10]" = "USB2_PORT_MAX"	# TYPE-A Port
+	register "usb2_ports[11]" = "USB2_PORT_MAX"	# TYPE-A Port
+
+	# USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT"	# TYPE-A Port
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT"	# TYPE-A Port
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT"	# TYPE-A Port
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT"	# TYPE-A Port
+	register "usb3_ports[4]" = "USB3_PORT_EMPTY"	# Disabled
+	register "usb3_ports[5]" = "USB3_PORT_EMPTY"	# Disabled
+
+	register "SsicPortEnable" = "1" # Enable SSIC for WWAN
 
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{ \
@@ -181,18 +205,12 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
 	}"
 
-	# PL2 override 25W
-	register "tdp_pl2_override" = "25"
-
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
 	# Enable/Disable VMX feature
 	register "VmxEnable" = "0"
 
-	# Use default SD card detect GPIO configuration
-	register "sdcard_cd_gpio_default" = "GPP_A7"
-
 	device cpu_cluster 0 on
 		device lapic 0 on end
 	end
@@ -202,23 +220,8 @@ chip soc/intel/skylake
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
-		device pci 15.0 on
-			chip drivers/i2c/generic
-				register "hid" = ""ELAN0001""
-				register "desc" = ""ELAN Touchscreen""
-				register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)"
-				device i2c 10 on end
-			end
-		end # I2C #0
-		device pci 15.1 on
-			chip drivers/i2c/generic
-				register "hid" = ""ELAN0000""
-				register "desc" = ""ELAN Touchpad""
-				register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)"
-				register "wake" = "GPE0_DW0_05"
-				device i2c 15 on end
-			end
-		end # I2C #1
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on  end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
 		device pci 16.0 on  end # Management Engine Interface 1
@@ -229,61 +232,14 @@ chip soc/intel/skylake
 		device pci 17.0 off end # SATA
 		device pci 19.0 on  end # UART #2
 		device pci 19.1 off end # I2C #5
-		device pci 19.2 on
-			chip drivers/i2c/nau8825
-				register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)"
-				register "jkdet_enable" = "1"
-				register "jkdet_pull_enable" = "1"
-				register "jkdet_pull_up" = "1"
-				register "jkdet_polarity" = "1"      # ActiveLow
-				register "vref_impedance" = "2"      # 125kOhm
-				register "micbias_voltage" = "6"     # 2.754
-				register "sar_threshold_num" = "4"
-				register "sar_threshold[0]" = "0x08"
-				register "sar_threshold[1]" = "0x12"
-				register "sar_threshold[2]" = "0x26"
-				register "sar_threshold[3]" = "0x73"
-				register "sar_hysteresis" = "0"
-				register "sar_voltage" = "6"
-				register "sar_compare_time" = "1"     # 1us
-				register "sar_sampling_time" = "1"    # 4us
-				register "short_key_debounce" = "3"   # 30ms
-				register "jack_insert_debounce" = "7" # 512ms
-				register "jack_eject_debounce" = "0"
-				device i2c 1a on end
-			end
-			chip drivers/i2c/generic
-				register "hid" = ""INT343B""
-				register "desc" = ""SSM4567 Left Speaker Amp""
-				register "uid" = "0"
-				register "device_present_gpio" = "GPP_E3"
-				device i2c 34 on end
-			end
-			chip drivers/i2c/generic
-				register "hid" = ""INT343B""
-				register "desc" = ""SSM4567 Right Speaker Amp""
-				register "uid" = "1"
-				register "device_present_gpio" = "GPP_E3"
-				device i2c 35 on end
-			end
-		end # I2C #4
-		device pci 1c.0 on
-			chip drivers/intel/wifi
-				register "wake" = "GPE0_DW0_16"
-				device pci 00.0 on end
-			end
-		end # PCI Express Port 1
-		device pci 1c.1 off end # PCI Express Port 2
-		device pci 1c.2 off end # PCI Express Port 3
-		device pci 1c.3 off end # PCI Express Port 4
-		device pci 1c.4 on  end # PCI Express Port 5
-		device pci 1c.5 off end # PCI Express Port 6
+		device pci 19.2 on  end
+		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
+		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.5 on  end # PCI Express Port 6 x1 SLOT3
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 off end # PCI Express Port 9
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.0 on  end # PCI Express Port 9  x1 WLAN
+		device pci 1d.1 on  end # PCI Express Port 10 x1 WIGIG
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 off end # GSPI #0
@@ -291,24 +247,10 @@ chip soc/intel/skylake
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO
 		device pci 1e.6 on  end # SDCard
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Interface
+		device pci 1f.0 on  end # LPC Interface
 		device pci 1f.1 on  end # P2SB
 		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on
-			chip drivers/generic/max98357a
-				register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
-				register "device_present_gpio" = "GPP_E3"
-				register "device_present_gpio_invert" = "1"
-				device generic 0 on end
-			end
-		end # Intel HDA
+		device pci 1f.3 on  end # Intel HDA
 		device pci 1f.4 on  end # SMBus
 		device pci 1f.5 on  end # PCH SPI
 		device pci 1f.6 off end # GbE
diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/gpio.h
index f8ee994b8f..5e251d846c 100644
--- a/src/mainboard/intel/kblrvp/gpio.h
+++ b/src/mainboard/intel/kblrvp/gpio.h
@@ -185,7 +185,7 @@ static const struct pad_config gpio_table[] = {
 /* PCH_BATLOW */	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 /* AC_PRESENT */	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 /* PCH_WAKE */		PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
-/* PCH_PWRBTN */	PAD_CFG_NF(GPD3, 20K_PD, DEEP, NF1),
+/* PCH_PWRBTN */	PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
 /* PM_SLP_S3# */	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 /* PM_SLP_S4# */	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 /* PM_SLP_SA# */	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
@@ -204,4 +204,4 @@ static const struct pad_config early_gpio_table[] = {
 
 #endif
 
-#endif
\ No newline at end of file
+#endif