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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-30 10:56:31 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-10 23:08:16 +0000 |
| commit | 8084b3856852f3fb3905e0fe4957b08518095d38 (patch) | |
| tree | c6aca7299eb82c0e6d5a2eba048a3373aa9fe9ca /src/mainboard/intel | |
| parent | b92df578b48911893a475b6f47ddfc574f63eac7 (diff) | |
| download | coreboot-8084b3856852f3fb3905e0fe4957b08518095d38.tar.xz | |
sb/intel/lynxpoint/sata: Always use AHCI mode
The other two modes are not used by any mainboard, and the code seems to
be copied from older southbridges. As the code looks incorrect, drop it.
Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/baskingridge/devicetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 6345090c7a..784c926d5f 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -41,8 +41,6 @@ chip northbridge/intel/haswell register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x4000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" # SuperIO range is 0x700-0x73f |