diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-07-18 23:02:18 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 07:38:32 +0100 |
| commit | af98062817e61f4dafd509fd768696a4250f1aa3 (patch) | |
| tree | 3a973cd3d84dc6e7d95b105abf262d163c74e23d /src/mainboard/intel | |
| parent | d8c7d73283676306e383fde4f42547d0ee3b0209 (diff) | |
| download | coreboot-af98062817e61f4dafd509fd768696a4250f1aa3.tar.xz | |
Revert "lynxpoint: Move ME lock down to ramstage"
This reverts commit ff81f50f0e4c068b64c4a5c7f5244196ecd24965.
Deferring this step until the finalize stage will allow us
to defer waiting for the MBP clear indicator and speeding
up the boot.
Change-Id: Ib8edffd06689e72875830cd68b5aedb7ac3b0559
Reviewed-on: https://gerrit.chromium.org/gerrit/62631
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4373
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/baskingridge/mainboard_smi.c | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/wtm2/mainboard_smi.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c index f24af67579..e543494b25 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/mainboard_smi.c @@ -84,6 +84,7 @@ int mainboard_smi_apmc(u8 apmc) return 0; } + intel_me_finalize_smm(); intel_pch_finalize_smm(); intel_northbridge_haswell_finalize_smm(); intel_cpu_haswell_finalize_smm(); diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c index bcc94d6f2b..3ffc68441d 100644 --- a/src/mainboard/intel/wtm2/mainboard_smi.c +++ b/src/mainboard/intel/wtm2/mainboard_smi.c @@ -60,6 +60,7 @@ int mainboard_smi_apmc(u8 apmc) return 0; } + intel_me_finalize_smm(); intel_pch_finalize_smm(); intel_northbridge_haswell_finalize_smm(); intel_cpu_haswell_finalize_smm(); |