Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT

All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.

If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.

chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M

Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton

Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

30 files changed, 0 insertions, 2867 deletions

diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig
deleted file mode 100644
index 9671fffc7e..0000000000
--- a/src/mainboard/intel/eagleheights/Kconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-if BOARD_INTEL_EAGLEHEIGHTS
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_INTEL_SOCKET_BGA956
-	select NORTHBRIDGE_INTEL_I3100
-	select SOUTHBRIDGE_INTEL_I3100
-	select SUPERIO_INTEL_I3100
-	select SUPERIO_SMSC_SMSCSUPERIO
-	select HAVE_OPTION_TABLE
-	select HAVE_HARD_RESET
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_1024
-
-config MAINBOARD_DIR
-	string
-	default intel/eagleheights
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "EagleHeights"
-
-config MMCONF_BASE_ADDRESS
-	hex
-	default 0xe0000000
-
-config IRQ_SLOT_COUNT
-	int
-	default 9
-
-config MAX_CPUS
-	int
-	default 4
-
-endif # BOARD_INTEL_EAGLEHEIGHTS
diff --git a/src/mainboard/intel/eagleheights/Kconfig.name b/src/mainboard/intel/eagleheights/Kconfig.name
deleted file mode 100644
index 95be5cbc13..0000000000
--- a/src/mainboard/intel/eagleheights/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_INTEL_EAGLEHEIGHTS
-	bool "EagleHeights"
diff --git a/src/mainboard/intel/eagleheights/Makefile.inc b/src/mainboard/intel/eagleheights/Makefile.inc
deleted file mode 100644
index f9621db6b3..0000000000
--- a/src/mainboard/intel/eagleheights/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-ramstage-y += cstates.c
diff --git a/src/mainboard/intel/eagleheights/acpi_tables.c b/src/mainboard/intel/eagleheights/acpi_tables.c
deleted file mode 100644
index cd914da7f7..0000000000
--- a/src/mainboard/intel/eagleheights/acpi_tables.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "ioapic.h"
-
-#define IO_APIC0 2
-#define IO_APIC1 3
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	unsigned int irq_start = 0;
-	device_t dev = 0;
-	unsigned char bus_isa;
-
-	/* Local Apic */
-	current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 1, 0);
-	// This one is for the second core... Will it hurt?
-	current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 2, 1);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC0, IO_APIC_ADDR, irq_start);
-	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC1, IO_APIC_ADDR + 0x10000, irq_start);
-	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
-	dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
-
-	if (dev) {
-		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-		bus_isa++;
-	} else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
-		bus_isa = 7;
-	}
-
-	/* Map ISA IRQ 0 to IRQ 2 */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, bus_isa, 0, 2, 0);
-
-	/* IRQ9 differs from ISA standard - ours is active high, level-triggered */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000d);
-
-	return current;
-}
diff --git a/src/mainboard/intel/eagleheights/board_info.txt b/src/mainboard/intel/eagleheights/board_info.txt
deleted file mode 100644
index b351b8e696..0000000000
--- a/src/mainboard/intel/eagleheights/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: eval
diff --git a/src/mainboard/intel/eagleheights/cmos.layout b/src/mainboard/intel/eagleheights/cmos.layout
deleted file mode 100644
index eace7e704e..0000000000
--- a/src/mainboard/intel/eagleheights/cmos.layout
+++ /dev/null
@@ -1,96 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007-2008 coresystems GmbH
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; version 2 of
-# the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392          3       r       0        unused
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-400          1       e       2        hyper_threading
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-409          1       e       1        power_on_after_fail
-#410          6       r       0        unused
-
-# coreboot config options: bootloader
-416        512       s       0        boot_devices
-#928         80       r       0        unused
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-#1000        24       r       0        amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     1     Emergency
-6     2     Alert
-6     3     Critical
-6     4     Error
-6     5     Warning
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/intel/eagleheights/cstates.c b/src/mainboard/intel/eagleheights/cstates.c
deleted file mode 100644
index f683756894..0000000000
--- a/src/mainboard/intel/eagleheights/cstates.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <arch/x86/include/arch/acpigen.h>
-
-int get_cst_entries(acpi_cstate_t **entries)
-{
-	return 0;
-}
diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c
deleted file mode 100644
index dd97837c3f..0000000000
--- a/src/mainboard/intel/eagleheights/debug.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <spd.h>
-
-static void print_reg(unsigned char index)
-{
-	unsigned char data;
-
-	outb(index, 0x2e);
-	data = inb(0x2f);
-	printk(BIOS_DEBUG, "0x%02x: 0x%02x\n", index, data);
-	return;
-}
-
-static inline void xbus_en(void)
-{
-	/* select the XBUS function in the SIO */
-	outb(0x07, 0x2e);
-	outb(0x0f, 0x2f);
-	outb(0x30, 0x2e);
-	outb(0x01, 0x2f);
-	return;
-}
-
-static void setup_func(unsigned char func)
-{
-	/* select the function in the SIO */
-	outb(0x07, 0x2e);
-	outb(func, 0x2f);
-	/* print out the regs */
-	print_reg(0x30);
-	print_reg(0x60);
-	print_reg(0x61);
-	print_reg(0x62);
-	print_reg(0x63);
-	print_reg(0x70);
-	print_reg(0x71);
-	print_reg(0x74);
-	print_reg(0x75);
-	return;
-}
-
-static inline void siodump(void)
-{
-	int i;
-	unsigned char data;
-
-	 printk(BIOS_DEBUG, "\n*** SERVER I/O REGISTERS ***\n");
-	for (i = 0x10; i <= 0x2d; i++) {
-		print_reg((unsigned char)i);
-	}
-#if 0
-	printk(BIOS_DEBUG, "\n*** XBUS REGISTERS ***\n");
-	setup_func(0x0f);
-	for (i = 0xf0; i <= 0xff; i++) {
-		print_reg((unsigned char)i);
-	}
-
-	printk(BIOS_DEBUG, "\n***  SERIAL 1 CONFIG REGISTERS ***\n");
-	setup_func(0x03);
-	print_reg(0xf0);
-
-	printk(BIOS_DEBUG, "\n***  SERIAL 2 CONFIG REGISTERS ***\n");
-	setup_func(0x02);
-	print_reg(0xf0);
-
-#endif
-	printk(BIOS_DEBUG, "\n***  GPIO REGISTERS ***\n");
-	setup_func(0x07);
-	for (i = 0xf0; i <= 0xf8; i++) {
-		print_reg((unsigned char)i);
-	}
-	printk(BIOS_DEBUG, "\n***  GPIO VALUES ***\n");
-	data = inb(0x68a);
-	printk(BIOS_DEBUG, "\nGPDO 4: 0x%02x", data);
-	data = inb(0x68b);
-	printk(BIOS_DEBUG, "\nGPDI 4: 0x%02x\n", data);
-
-#if 0
-
-	printk(BIOS_DEBUG, "\n***  WATCHDOG TIMER REGISTERS ***\n");
-	setup_func(0x0a);
-	print_reg(0xf0);
-
-	printk(BIOS_DEBUG, "\n***  FAN CONTROL REGISTERS ***\n");
-	setup_func(0x09);
-	print_reg(0xf0);
-	print_reg(0xf1);
-
-	printk(BIOS_DEBUG, "\n***  RTC REGISTERS ***\n");
-	setup_func(0x10);
-	print_reg(0xf0);
-	print_reg(0xf1);
-	print_reg(0xf3);
-	print_reg(0xf6);
-	print_reg(0xf7);
-	print_reg(0xfe);
-	print_reg(0xff);
-
-	printk(BIOS_DEBUG, "\n***  HEALTH MONITORING & CONTROL REGISTERS ***\n");
-	setup_func(0x14);
-	print_reg(0xf0);
-#endif
-	return;
-}
-
-static inline void dump_bar14(unsigned dev)
-{
-	int i;
-	unsigned long bar;
-
-	printk(BIOS_DEBUG, "BAR 14 Dump\n");
-
-	bar = pci_read_config32(dev, 0x14);
-	for(i = 0; i <= 0x300; i+=4) {
-#if 0
-		unsigned char val;
-		if ((i & 0x0f) == 0)
-			printk(BIOS_DEBUG, "%02x:", i);
-		val = pci_read_config8(dev, i);
-#endif
-		if((i%4)==0)
-			printk(BIOS_DEBUG, "\n%04x ", i);
-		printk(BIOS_DEBUG, "%08x ", read32(bar + i));
-	}
-	printk(BIOS_DEBUG, "\n");
-}
-
-static inline void dump_spd_registers(void)
-{
-	unsigned device;
-	device = DIMM0;
-	while(device <= DIMM7) {
-		int status = 0;
-		int i;
-		printk(BIOS_DEBUG, "\ndimm %02x", device);
-
-		for(i = 0; (i < 256); i++) {
-			if ((i % 16) == 0)
-				printk(BIOS_DEBUG, "\n%02x: ", i);
-			status = smbus_read_byte(device, i);
-			if (status < 0) {
-				printk(BIOS_DEBUG, "bad device: %d\n", -status);
-				break;
-			}
-			printk(BIOS_DEBUG, "%02x ", status);
-		}
-		device++;
-		printk(BIOS_DEBUG, "\n");
-	}
-}
-
-static inline void dump_ipmi_registers(void)
-{
-	unsigned device;
-	device = 0x42;
-	while(device <= 0x42) {
-		int status = 0;
-		int i;
-		printk(BIOS_DEBUG, "\nipmi %02x", device);
-
-		for(i = 0; (i < 8); i++) {
-			status = smbus_read_byte(device, 2);
-			if (status < 0) {
-				printk(BIOS_DEBUG, "bad device: %d\n", -status);
-				break;
-			}
-			printk(BIOS_DEBUG, "%02x ", status);
-		}
-		device++;
-		printk(BIOS_DEBUG, "\n");
-	}
-}
diff --git a/src/mainboard/intel/eagleheights/devicetree.cb b/src/mainboard/intel/eagleheights/devicetree.cb
deleted file mode 100644
index 8d1549af19..0000000000
--- a/src/mainboard/intel/eagleheights/devicetree.cb
+++ /dev/null
@@ -1,72 +0,0 @@
-chip northbridge/intel/i3100
-        device domain 0 on
-                device pci 00.0 on end # IMCH
-                device pci 00.1 on end # IMCH error status
-                device pci 01.0 on end # IMCH EDMA engine
-                device pci 02.0 on end # PCIe port A/A0
-                device pci 03.0 on end # PCIe port A1
-                chip southbridge/intel/i3100
-                        # PIRQ line -> legacy IRQ mappings
-			register "pirq_a_d" = "0x8b808a8a"
-                        register "pirq_e_h" = "0x85808080"
-
-                        device pci 1c.0 on end # PCIe port B0
-                        device pci 1c.1 off end # PCIe port B1
-                        device pci 1c.2 off end # PCIe port B2
-                        device pci 1c.3 off end # PCIe port B3
-                        device pci 1d.0 on end # USB (UHCI) 1
-                        device pci 1d.1 on end # USB (UHCI) 2
-                        device pci 1d.7 on end # USB (EHCI)
-                        device pci 1e.0 on end # PCI bridge
-                        device pci 1f.0 on     # LPC bridge
-                                chip superio/intel/i3100
-                                        device pnp 4e.4 on # Com1
-                                                 io 0x60 = 0x3f8
-                                                irq 0x70 = 4
-                                        end
-                                        device pnp 4e.5 on # Com2
-                                                 io 0x60 = 0x2f8
-                                                irq 0x70 = 3
-                                        end
-                                end
-				chip superio/smsc/smscsuperio
-					device pnp 2e.0 off	# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.2 off	# Serial Port 4
-						io 0x60 = 0x2e8
-						irq 0x70 = 3
-					end
-					device pnp 2e.3 on	# Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-						drq 0x74 = 2
-					end
-					device pnp 2e.4 off	# Serial Port 3
-						io 0x60 = 0x3e8
-						irq 0x70 = 4
-					end
-					device pnp 2e.7 on	# PS/2 Keyboard / Mouse
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1    # PS/2 keyboard interrupt
-						irq 0x72 = 12   # PS/2 mouse interrupt
-					end
-					device pnp 2e.a off     # Runtime registers
-					       io 0x60 = 0x600
-					end
-				end
-                        end
-                        device pci 1f.2 on end # SATA
-                        device pci 1f.3 on end # SMBus
-			device pci 1f.4 on end # Performance counters
-                end
-        end
-        device cpu_cluster 0 on
-                chip cpu/intel/socket_BGA956
-                        device lapic 0 on end
-                end
-        end
-end
diff --git a/src/mainboard/intel/eagleheights/dsdt.asl b/src/mainboard/intel/eagleheights/dsdt.asl
deleted file mode 100644
index 4c98e54637..0000000000
--- a/src/mainboard/intel/eagleheights/dsdt.asl
+++ /dev/null
@@ -1,1041 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001)
-{
-	Scope (\_PR)
-	{
-		Processor (CPU1, 0x01, 0x00000810, 0x06)
-		{
-			OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
-			Name (NCPU, 0x80)
-			Name (TYPE, 0x80000000)
-			Name (HNDL, 0x80000000)
-			Name (CFGD, 0x80000000)
-			Name (TBLD, 0x80)
-			Method (_PDC, 1, NotSerialized)
-			{
-			}
-		}
-	}
-
-	Scope (\_PR)
-	{
-		Processor (CPU2, 0x02, 0x00000000, 0x00)
-		{
-			OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
-			Name (NCPU, 0x80)
-			Name (TYPE, 0x80000000)
-			Name (HNDL, 0x80000000)
-			Name (CFGD, 0x80000000)
-			Name (TBLD, 0x80)
-			Method (_PDC, 1, NotSerialized)
-			{
-			}
-		}
-	}
-
-	/* For now only define 2 power states:
-	*  - S0 which is fully on
-	*  - S5 which is soft off
-	* Any others would involve declaring the wake up methods.
-	*/
-	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
-	Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
-
-	Name (PICM, 0x00)
-	Method (_PIC, 1, NotSerialized)
-	{
-		Store (Arg0, PICM)
-	}
-
-	/* System bus */
-	Scope (\_SB)
-	{
-		/* Routing PCI0 */
-		Name (PR00, Package (0x0E)
-		{
-		Package (0x04){0x0001FFFF,0x00,LNKA,0x00}, /* EDMA INTA# */
-		Package (0x04){0x0002FFFF,0x00,LNKA,0x00}, /* PCIe port A */
-		Package (0x04){0x0002FFFF,0x01,LNKB,0x00},
-		Package (0x04){0x0002FFFF,0x02,LNKC,0x00},
-		Package (0x04){0x0002FFFF,0x03,LNKD,0x00},
-		Package (0x04){0x0003FFFF,0x00,LNKA,0x00}, /* PCIe port A1 */
-		Package (0x04){0x0003FFFF,0x01,LNKB,0x00},
-		Package (0x04){0x0003FFFF,0x02,LNKC,0x00},
-		Package (0x04){0x0003FFFF,0x03,LNKD,0x00},
-		Package (0x04){0x001CFFFF,0x00,LNKE,0x00}, /* PCIe port B */
-			Package (0x04){0x001DFFFF,0x00,LNKH,0x00}, /* UHCI/EHCI INTA# */
-			Package (0x04){0x001DFFFF,0x01,LNKD,0x00}, /* UHCI INTB# */
-		Package (0x04){0x001FFFFF,0x01,LNKD,0x00}, /* SATA/SMBUS INTB# */
-			Package (0x04){0x001FFFFF,0x03,LNKA,0x00}  /* CHAP INTD# */
-		})
-		Name (AR00, Package (0x0E)
-		{
-		Package (0x04){0x0001FFFF,0x00,0x00,0x10}, /* EDMA INTA# */
-		Package (0x04){0x0002FFFF,0x00,0x00,0x10}, /* PCIe port A0 */
-		Package (0x04){0x0002FFFF,0x01,0x00,0x11},
-		Package (0x04){0x0002FFFF,0x02,0x00,0x12},
-		Package (0x04){0x0002FFFF,0x03,0x00,0x13},
-		Package (0x04){0x0003FFFF,0x00,0x00,0x10}, /* PCIe port A1 */
-		Package (0x04){0x0003FFFF,0x01,0x00,0x11},
-		Package (0x04){0x0003FFFF,0x02,0x00,0x12},
-		Package (0x04){0x0003FFFF,0x03,0x00,0x13},
-		Package (0x04){0x001CFFFF,0x00,0x00,0x14}, /* PCIe port B */
-			Package (0x04){0x001DFFFF,0x00,0x00,0x17}, /* UHCI/EHCI INTA# */
-			Package (0x04){0x001DFFFF,0x01,0x00,0x13}, /* UHCI INTB# */
-		Package (0x04){0x001FFFFF,0x01,0x00,0x13}, /* SATA/SMBUS INTB# */
-			Package (0x04){0x001FFFFF,0x0D,0x00,0x10}  /* CHAP INTD# */
-		})
-	/* Routing PCIe Port A */
-		Name (PR0A, Package (0x04)
-		{
-			Package (0x04){0xFFFF,0x00,LNKA,0x00},
-			Package (0x04){0xFFFF,0x01,LNKB,0x00},
-			Package (0x04){0xFFFF,0x02,LNKC,0x00},
-			Package (0x04){0xFFFF,0x03,LNKD,0x00}
-		})
-		Name (AR0A, Package (0x04)
-		{
-			Package (0x04){0xFFFF,0x00,0x00,0x10},
-			Package (0x04){0xFFFF,0x01,0x00,0x11},
-			Package (0x04){0xFFFF,0x02,0x00,0x12},
-			Package (0x04){0xFFFF,0x03,0x00,0x13}
-		})
-	/* Routing PCIe Port B */
-		Name (PR0B, Package (0x04)
-		{
-			Package (0x04){0xFFFF,0x00,LNKA,0x00},
-			Package (0x04){0xFFFF,0x01,LNKB,0x00},
-			Package (0x04){0xFFFF,0x02,LNKC,0x00},
-			Package (0x04){0xFFFF,0x03,LNKD,0x00}
-		})
-		Name (AR0B, Package (0x04)
-		{
-			Package (0x04){0xFFFF,0x00,0x00,0x10},
-			Package (0x04){0xFFFF,0x01,0x00,0x11},
-			Package (0x04){0xFFFF,0x02,0x00,0x12},
-			Package (0x04){0xFFFF,0x03,0x00,0x13}
-		})
-	/* Routing Bus PCI */
-	Name (PR01, Package (0x04)
-		{
-		Package (0x04){0x0000FFFF,0x00,LNKA,0x00},
-		Package (0x04){0x0000FFFF,0x01,LNKB,0x00},
-		Package (0x04){0x0000FFFF,0x02,LNKC,0x00},
-		Package (0x04){0x0000FFFF,0x03,LNKD,0x00},
-	})
-	Name (AR01, Package (0x04)
-		{
-		Package (0x04){0x0000FFFF,0x00,0x00,0x10},
-		Package (0x04){0x0000FFFF,0x01,0x00,0x11},
-		Package (0x04){0x0000FFFF,0x02,0x00,0x12},
-		Package (0x04){0x0000FFFF,0x03,0x00,0x13},
-	})
-
-		Name (PRSA, ResourceTemplate ()
-		{
-			IRQ (Level, ActiveLow, Shared, )
-				{3,4,5,6,7,10,11,12,14,15}
-		})
-		Alias (PRSA, PRSB)
-		Alias (PRSA, PRSC)
-		Alias (PRSA, PRSD)
-		Alias (PRSA, PRSE)
-		Alias (PRSA, PRSF)
-		Alias (PRSA, PRSG)
-		Alias (PRSA, PRSH)
-
-	Device (PCI0)
-	{
-		Name (_HID, EisaId ("PNP0A08"))
-		Name (_CID, EisaId ("PNP0A03"))
-		Name (_ADR, 0x00)
-		Name (_SEG, 0x00)
-		Name (_UID, 0x00)
-		Name (_BBN, 0x00)
-
-		Name (SUPP, 0) /* PCI _OSC Support Field Value */
-		Name (CTRL, 0) /* PCI _OSC Control Field Value */
-
-		Method (_OSC, 4)
-		{
-			/* Check for PCI/PCI-X/PCIe GUID */
-			If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
-			{
-				/* Let OS control everything */
-				Return (Arg3)
-			}
-			Else
-			{
-				/* Unrecognized UUID, so set bit 2 of Arg3 to 1 */
-				CreateDWordField (Arg3, 0, CDW1)
-				Or (CDW1, 4, CDW1)
-				Return (Arg3)
-			}
-		} /* End _OSC */
-
-			Method (_PRT, 0, NotSerialized)
-			{
-				If (PICM)
-				{
-					Return (AR00)
-				}
-
-				Return (PR00)
-			}
-
-		/* PCI Express Port A */
-		Device (EPA0)
-			{
-				Name (_ADR, 0x00020000)
-				Method (_PRT, 0, NotSerialized)
-				{
-					If (PICM)
-					{
-						Return (AR0A)
-					}
-
-					Return (PR0A)
-				}
-			}
-
-		/* PCI Express Port A1 */
-			Device (EPA1)
-			{
-				Name (_ADR, 0x00030000)
-				Method (_PRT, 0, NotSerialized)
-				{
-					If (PICM)
-					{
-						Return (AR0A)
-					}
-
-					Return (PR0A)
-				}
-			}
-
-		/* PCI Express Port B0 */
-			Device (EPB0)
-			{
-				Name (_ADR, 0x001C0000)
-				Method (_PRT, 0, NotSerialized)
-				{
-					If (PICM)
-					{
-						Return (AR0B)
-					}
-
-					Return (PR0B)
-				}
-			}
-
-		/* PCI Bridge */
-			Device (P0P1)
-			{
-				Name (_ADR, 0x001E0000)
-
-				Method (_PRT, 0, NotSerialized)
-				{
-					If (PICM)
-					{
-						Return (AR01)
-					}
-
-					Return (PR01)
-				}
-			}
-
-		/* LPC I/F Bridge */
-		Device (ISA) {
-			Name (_ADR, 0x001F0000)
-
-				/* MMCONF */
-				Device (^PCIE)
-				{
-					Name (_HID, EisaId ("PNP0C02"))
-					Name (_UID, 0x11)
-					Name (CRS, ResourceTemplate ()
-					{
-						Memory32Fixed (ReadOnly,
-							0xE0000000,         // Address Base
-							0x10000000,         // Address Length
-							_Y10)
-					})
-					Method (_CRS, 0, NotSerialized)
-					{
-						CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._BAS, BAS1)
-						CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._LEN, LEN1)
-						Store (0xE0000000, BAS1)
-						Store (0x10000000, LEN1)
-						Return (CRS)
-					}
-				}
-
-		/* PIC */
-				Device (PIC)
-				{
-			Name (_HID, EisaId ("PNP0000"))
-			Name (_CRS, ResourceTemplate()
-			{
-				IO (Decode16,
-				0x0020,
-				0x0020,
-				0x00,
-				0x02,
-				)
-			IO (Decode16,
-				0x00A0,
-				0x00A0,
-				0x00,
-				0x02,
-				)
-			IRQNoFlags ()
-				{2}
-			})
-				}
-
-		/* Real time clock */
-				Device (RTC0)
-				{
-					Name (_HID, EisaId ("PNP0B00"))
-					Name (_CRS, ResourceTemplate ()
-					{
-						IO (Decode16,
-				0x0070,
-				0x0070,
-				0x00,
-				0x02)
-						IRQNoFlags ()
-				{8}
-					})
-				}
-
-				Device (UAR1)
-				{
-					Name (_UID, 0x01)
-					Name (_HID, EisaId ("PNP0501"))
-
-					Method (_PRS, 0, NotSerialized)
-					{
-						Return (CMPR)
-					}
-
-					Name (CMPR, ResourceTemplate ()
-					{
-						StartDependentFn (0x00, 0x00)
-						{
-							IO (Decode16,0x03F8,0x03F8,0x01,0x08)
-							IRQNoFlags () {4}
-							DMA (Compatibility, NotBusMaster, Transfer8) {}
-						}
-						StartDependentFnNoPri ()
-						{
-							IO (Decode16,0x03F8,0x03F8,0x01,0x08)
-							IRQNoFlags () {3,4,5,6,7,10,11,12}
-							DMA (Compatibility, NotBusMaster, Transfer8) {}
-						}
-						StartDependentFnNoPri ()
-						{
-							IO (Decode16,0x02F8,0x02F8,0x01,0x08)
-							IRQNoFlags () {3,4,5,6,7,10,11,12}
-				DMA (Compatibility, NotBusMaster, Transfer8) {}
-						}
-						StartDependentFnNoPri ()
-						{
-							IO (Decode16,0x03E8,0x03E8,0x01,0x08)
-							IRQNoFlags () {3,4,5,6,7,10,11,12}
-				DMA (Compatibility, NotBusMaster, Transfer8) {}
-						}
-						StartDependentFnNoPri ()
-						{
-							IO (Decode16,0x02E8,0x02E8,0x01,0x08)
-							IRQNoFlags () {3,4,5,6,7,10,11,12}
-							DMA (Compatibility, NotBusMaster, Transfer8) {}
-						}
-						EndDependentFn ()
-					})
-				}
-
-		/* PS/2 keyboard (seems to be important for WinXP install) */
-		Device (KBD)
-		{
-			Name (_HID, EisaId ("PNP0303"))
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (0x0f)
-			}
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (TMP, ResourceTemplate () {
-							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
-				IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
-				IRQNoFlags () {1}
-			})
-			Return (TMP)
-			}
-		}
-
-		/* PS/2 mouse */
-		Device (MOU)
-		{
-			Name (_HID, EisaId ("PNP0F13"))
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (0x0f)
-			}
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (TMP, ResourceTemplate () {
-				IRQNoFlags () {12}
-			})
-			Return (TMP)
-			}
-		}
-
-		/* COM ports of SIO */
-		Device(SIO) {
-				Name (_ADR, 0x4E)
-				OperationRegion (PT4E, SystemIO, 0x4E, 0x02)
-				Field (PT4E, ByteAcc, NoLock, Preserve)
-				{
-					PO4E,   8,
-					PO4F,   8
-				}
-
-				IndexField (PO4E, PO4F, ByteAcc, NoLock, Preserve)
-				{
-							Offset (0x07),
-					ILDN,   8,
-							Offset (0x28),
-					SIUI,   8,
-					SIUC,   8,
-							Offset (0x30),
-					IACT,   8,
-							Offset (0x60),
-					IIOH,   8,
-					IIOL,   8,
-							Offset (0x70),
-					IINT,   8
-				}
-
-				Method (IENF, 0, NotSerialized)
-				{
-					Store (0x80, PO4E)
-					Store (0x86, PO4E)
-				}
-
-				Method (IEXF, 0, NotSerialized)
-				{
-					Store (0x68, PO4E)
-					Store (0x08, PO4E)
-				}
-
-				Device (COM1)
-				{
-					Name (_UID, 0x03)
-					Name (_HID, EisaId ("PNP0501"))
-					Method (_STA, 0, NotSerialized)
-					{
-						IENF ()
-						Store (0x04, ILDN)
-						Store (IACT, Local0)
-						IEXF ()
-						If (LEqual (Local0, 0xFF))
-						{
-							Return (0x00)
-						}
-
-						If (LEqual (Local0, One))
-						{
-							Return (0x0F)
-						}
-						Else
-						{
-							Return (0x0D)
-						}
-					}
-
-					Method (_DIS, 0, NotSerialized)
-					{
-						IENF ()
-						Store (0x04, ILDN)
-						Store (Zero, IACT)
-						IEXF ()
-					}
-
-					Method (_CRS, 0, NotSerialized)
-					{
-						Name (BFU1, ResourceTemplate ()
-						{
-							IO (Decode16,
-								0x03F8,             // Range Minimum
-								0x03F8,             // Range Maximum
-								0x08,               // Alignment
-								0x08,               // Length
-								_Y03)
-							IRQNoFlags (_Y04)
-								{5}
-						})
-						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MIN, IMIN)
-						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MAX, IMAX)
-						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y04._INT, IRQ0)
-						IENF ()
-						Store (0x04, ILDN)
-						Store (IIOH, Local0)
-						ShiftLeft (Local0, 0x08, Local1)
-						Store (IIOL, Local0)
-						Add (Local1, Local0, Local0)
-						Store (Local0, IMIN)
-						Store (Local0, IMAX)
-						Store (IINT, Local0)
-						IEXF ()
-						Store (0x01, Local1)
-						ShiftLeft (Local1, Local0, IRQ0)
-						Return (BFU1)
-					}
-
-					Name (_PRS, ResourceTemplate ()
-					{
-						StartDependentFnNoPri ()
-						{
-							IO (Decode16,
-								0x03F8,             // Range Minimum
-								0x03F8,             // Range Maximum
-								0x08,               // Alignment
-								0x08,               // Length
-								)
-							IRQNoFlags ()
-								{5}
-						}
-						StartDependentFnNoPri ()
-						{
-							IO (Decode16,
-								0x02F8,             // Range Minimum
-								0x02F8,             // Range Maximum
-								0x08,               // Alignment
-								0x08,               // Length
-								)
-							IRQNoFlags ()
-								{9}
-						}
-				EndDependentFn ()
-					})
-					Method (_SRS, 1, NotSerialized)
-					{
-						CreateByteField (Arg0, 0x02, IOLO)
-						CreateByteField (Arg0, 0x03, IOHI)
-						CreateWordField (Arg0, 0x09, IRQ0)
-						IENF ()
-						Store (0x04, ILDN)
-						Store (Zero, IACT)
-						Store (IOLO, IIOL)
-						Store (IOHI, IIOH)
-						FindSetRightBit (IRQ0, Local0)
-						If (LGreater (Local0, 0x00))
-						{
-							Decrement (Local0)
-						}
-
-						Store (Local0, IINT)
-						Store (One, IACT)
-						IEXF ()
-					}
-				} /* COM1 */
-
-				Device (COM2)
-				{
-					Name (_UID, 0x04)
-					Name (_HID, EisaId ("PNP0501"))
-					Method (_STA, 0, NotSerialized)
-					{
-						IENF ()
-						Store (0x05, ILDN)
-						Store (IACT, Local0)
-						IEXF ()
-						If (LEqual (Local0, 0xFF))
-						{
-							Return (0x00)
-						}
-
-						If (LEqual (Local0, One))
-						{
-							Return (0x0F)
-						}
-						Else
-						{
-							Return (0x0D)
-						}
-					}
-
-					Method (_DIS, 0, NotSerialized)
-					{
-						IENF ()
-						Store (0x05, ILDN)
-						Store (Zero, IACT)
-						IEXF ()
-					}
-
-					Method (_CRS, 0, NotSerialized)
-					{
-						Name (BFU1, ResourceTemplate ()
-						{
-							IO (Decode16,
-								0x03F8,             // Range Minimum
-								0x03F8,             // Range Maximum
-								0x08,               // Alignment
-								0x08,               // Length
-								_Y05)
-							IRQNoFlags (_Y06)
-								{9}
-						})
-						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MIN, IMIN)
-						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MAX, IMAX)
-						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y06._INT, IRQ0)
-						IENF ()
-						Store (0x05, ILDN)
-						Store (IIOH, Local0)
-						ShiftLeft (Local0, 0x08, Local1)
-						Store (IIOL, Local0)
-						Add (Local1, Local0, Local0)
-						Store (Local0, IMIN)
-						Store (Local0, IMAX)
-						Store (IINT, Local0)
-						IEXF ()
-						Store (0x01, Local1)
-						ShiftLeft (Local1, Local0, IRQ0)
-						Return (BFU1)
-					}
-
-					Name (_PRS, ResourceTemplate ()
-					{
-						StartDependentFnNoPri ()
-						{
-							IO (Decode16,
-								0x03F8,             // Range Minimum
-								0x03F8,             // Range Maximum
-								0x08,               // Alignment
-								0x08,               // Length
-								)
-							IRQNoFlags ()
-								{5}
-						}
-						StartDependentFnNoPri ()
-						{
-							IO (Decode16,
-								0x02F8,             // Range Minimum
-								0x02F8,             // Range Maximum
-								0x08,               // Alignment
-								0x08,               // Length
-								)
-							IRQNoFlags ()
-								{9}
-						}
-						EndDependentFn ()
-					})
-					Method (_SRS, 1, NotSerialized)
-					{
-						CreateByteField (Arg0, 0x02, IOLO)
-						CreateByteField (Arg0, 0x03, IOHI)
-						CreateWordField (Arg0, 0x09, IRQ0)
-						IENF ()
-						Store (0x05, ILDN)
-						Store (Zero, IACT)
-						Store (IOLO, IIOL)
-						Store (IOHI, IIOH)
-						FindSetRightBit (IRQ0, Local0)
-						If (LGreater (Local0, 0x00))
-						{
-							Decrement (Local0)
-						}
-
-						Store (Local0, IINT)
-						Store (One, IACT)
-						IEXF ()
-					}
-				} /* COM2 */
-		} /* Device SIO */
-		} /* Device ISA */
-	} /* Device PCI 0*/
-	} /* Scope SB */
-
-	OperationRegion (_SB.PCI0.ISA.PIX0, PCI_Config, 0x60, 0x0C)
-	Field (\_SB.PCI0.ISA.PIX0, ByteAcc, NoLock, Preserve)
-	{
-		PIRA,   8,
-		PIRB,   8,
-		PIRC,   8,
-		PIRD,   8,
-				Offset (0x08),
-		PIRE,   8,
-		PIRF,   8,
-		PIRG,   8,
-		PIRH,   8
-	}
-
-	Scope (_SB)
-	{
-		Name (BUFA, ResourceTemplate ()
-		{
-			IRQ (Level, ActiveLow, Shared, _Y1C)
-				{15}
-		})
-		CreateWordField (BUFA, \_SB._Y1C._INT, IRA0)
-		Device (LNKA)
-		{
-			Name (_HID, EisaId ("PNP0C0F"))
-			Name (_UID, 0x01)
-			Method (_STA, 0, NotSerialized)
-			{
-				And (PIRA, 0x80, Local0)
-				If (Local0)
-				{
-					Return (0x09)
-				}
-				Else
-				{
-					Return (0x0B)
-				}
-			}
-
-			Method (_PRS, 0, NotSerialized)
-			{
-				Return (PRSA)
-			}
-
-			Method (_DIS, 0, NotSerialized)
-			{
-				Or (PIRA, 0x80, PIRA)
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				And (PIRA, 0x0F, Local0)
-				ShiftLeft (0x01, Local0, IRA0)
-				Return (BUFA)
-			}
-
-			Method (_SRS, 1, NotSerialized)
-			{
-				CreateWordField (Arg0, 0x01, IRA)
-				FindSetRightBit (IRA, Local0)
-				Decrement (Local0)
-				Store (Local0, PIRA)
-			}
-		}
-
-		Device (LNKB)
-		{
-			Name (_HID, EisaId ("PNP0C0F"))
-			Name (_UID, 0x02)
-			Method (_STA, 0, NotSerialized)
-			{
-				And (PIRB, 0x80, Local0)
-				If (Local0)
-				{
-					Return (0x09)
-				}
-				Else
-				{
-					Return (0x0B)
-				}
-			}
-
-			Method (_PRS, 0, NotSerialized)
-			{
-				Return (PRSB)
-			}
-
-			Method (_DIS, 0, NotSerialized)
-			{
-				Or (PIRB, 0x80, PIRB)
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				And (PIRB, 0x0F, Local0)
-				ShiftLeft (0x01, Local0, IRA0)
-				Return (BUFA)
-			}
-
-			Method (_SRS, 1, NotSerialized)
-			{
-				CreateWordField (Arg0, 0x01, IRA)
-				FindSetRightBit (IRA, Local0)
-				Decrement (Local0)
-				Store (Local0, PIRB)
-			}
-		}
-
-		Device (LNKC)
-		{
-			Name (_HID, EisaId ("PNP0C0F"))
-			Name (_UID, 0x03)
-			Method (_STA, 0, NotSerialized)
-			{
-				And (PIRC, 0x80, Local0)
-				If (Local0)
-				{
-					Return (0x09)
-				}
-				Else
-				{
-					Return (0x0B)
-				}
-			}
-
-			Method (_PRS, 0, NotSerialized)
-			{
-				Return (PRSC)
-			}
-
-			Method (_DIS, 0, NotSerialized)
-			{
-				Or (PIRC, 0x80, PIRC)
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				And (PIRC, 0x0F, Local0)
-				ShiftLeft (0x01, Local0, IRA0)
-				Return (BUFA)
-			}
-
-			Method (_SRS, 1, NotSerialized)
-			{
-				CreateWordField (Arg0, 0x01, IRA)
-				FindSetRightBit (IRA, Local0)
-				Decrement (Local0)
-				Store (Local0, PIRC)
-			}
-		}
-
-		Device (LNKD)
-		{
-			Name (_HID, EisaId ("PNP0C0F"))
-			Name (_UID, 0x04)
-			Method (_STA, 0, NotSerialized)
-			{
-				And (PIRD, 0x80, Local0)
-				If (Local0)
-				{
-					Return (0x09)
-				}
-				Else
-				{
-					Return (0x0B)
-				}
-			}
-
-			Method (_PRS, 0, NotSerialized)
-			{
-				Return (PRSD)
-			}
-
-			Method (_DIS, 0, NotSerialized)
-			{
-				Or (PIRD, 0x80, PIRD)
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				And (PIRD, 0x0F, Local0)
-				ShiftLeft (0x01, Local0, IRA0)
-				Return (BUFA)
-			}
-
-			Method (_SRS, 1, NotSerialized)
-			{
-				CreateWordField (Arg0, 0x01, IRA)
-				FindSetRightBit (IRA, Local0)
-				Decrement (Local0)
-				Store (Local0, PIRD)
-			}
-		}
-
-		Device (LNKE)
-		{
-			Name (_HID, EisaId ("PNP0C0F"))
-			Name (_UID, 0x05)
-			Method (_STA, 0, NotSerialized)
-			{
-				And (PIRE, 0x80, Local0)
-				If (Local0)
-				{
-					Return (0x09)
-				}
-				Else
-				{
-					Return (0x0B)
-				}
-			}
-
-			Method (_PRS, 0, NotSerialized)
-			{
-				Return (PRSE)
-			}
-
-			Method (_DIS, 0, NotSerialized)
-			{
-				Or (PIRE, 0x80, PIRE)
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				And (PIRE, 0x0F, Local0)
-				ShiftLeft (0x01, Local0, IRA0)
-				Return (BUFA)
-			}
-
-			Method (_SRS, 1, NotSerialized)
-			{
-				CreateWordField (Arg0, 0x01, IRA)
-				FindSetRightBit (IRA, Local0)
-				Decrement (Local0)
-				Store (Local0, PIRE)
-			}
-		}
-
-		Device (LNKF)
-		{
-			Name (_HID, EisaId ("PNP0C0F"))
-			Name (_UID, 0x06)
-			Method (_STA, 0, NotSerialized)
-			{
-				And (PIRF, 0x80, Local0)
-				If (Local0)
-				{
-					Return (0x09)
-				}
-				Else
-				{
-					Return (0x0B)
-				}
-			}
-
-			Method (_PRS, 0, NotSerialized)
-			{
-				Return (PRSF)
-			}
-
-			Method (_DIS, 0, NotSerialized)
-			{
-				Or (PIRF, 0x80, PIRF)
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				And (PIRF, 0x0F, Local0)
-				ShiftLeft (0x01, Local0, IRA0)
-				Return (BUFA)
-			}
-
-			Method (_SRS, 1, NotSerialized)
-			{
-				CreateWordField (Arg0, 0x01, IRA)
-				FindSetRightBit (IRA, Local0)
-				Decrement (Local0)
-				Store (Local0, PIRF)
-			}
-		}
-
-		Device (LNKG)
-		{
-			Name (_HID, EisaId ("PNP0C0F"))
-			Name (_UID, 0x07)
-			Method (_STA, 0, NotSerialized)
-			{
-				And (PIRG, 0x80, Local0)
-				If (Local0)
-				{
-					Return (0x09)
-				}
-				Else
-				{
-					Return (0x0B)
-				}
-			}
-
-			Method (_PRS, 0, NotSerialized)
-			{
-				Return (PRSG)
-			}
-
-			Method (_DIS, 0, NotSerialized)
-			{
-				Or (PIRG, 0x80, PIRG)
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				And (PIRG, 0x0F, Local0)
-				ShiftLeft (0x01, Local0, IRA0)
-				Return (BUFA)
-			}
-
-			Method (_SRS, 1, NotSerialized)
-			{
-				CreateWordField (Arg0, 0x01, IRA)
-				FindSetRightBit (IRA, Local0)
-				Decrement (Local0)
-				Store (Local0, PIRG)
-			}
-		}
-
-		Device (LNKH)
-		{
-			Name (_HID, EisaId ("PNP0C0F"))
-			Name (_UID, 0x08)
-			Method (_STA, 0, NotSerialized)
-			{
-				And (PIRH, 0x80, Local0)
-				If (Local0)
-				{
-					Return (0x09)
-				}
-				Else
-				{
-					Return (0x0B)
-				}
-			}
-
-			Method (_PRS, 0, NotSerialized)
-			{
-				Return (PRSH)
-			}
-
-			Method (_DIS, 0, NotSerialized)
-			{
-				Or (PIRH, 0x80, PIRH)
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				And (PIRH, 0x0F, Local0)
-				ShiftLeft (0x01, Local0, IRA0)
-				Return (BUFA)
-			}
-
-			Method (_SRS, 1, NotSerialized)
-			{
-				CreateWordField (Arg0, 0x01, IRA)
-				FindSetRightBit (IRA, Local0)
-				Decrement (Local0)
-				Store (Local0, PIRH)
-			}
-		}
-	}
-}
diff --git a/src/mainboard/intel/eagleheights/fadt.c b/src/mainboard/intel/eagleheights/fadt.c
deleted file mode 100644
index eaea7f71e3..0000000000
--- a/src/mainboard/intel/eagleheights/fadt.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-#include <cpu/x86/smm.h>
-
-#define ACPI_PM1_STS        (pmbase + 0x00)
-#define ACPI_PM1_EN         (pmbase + 0x02)
-#define ACPI_PM1_CNT        (pmbase + 0x04)
-#define ACPI_PM1_TMR        (pmbase + 0x08)
-#define ACPI_PROC_CNT       (pmbase + 0x10)
-#define ACPI_LV2            (pmbase + 0x14)
-#define ACPI_GPE0_STS       (pmbase + 0x28)
-#define ACPI_GPE0_EN        (pmbase + 0x2C)
-#define ACPI_SMI_EN         (pmbase + 0x30)
-#define ACPI_SMI_STS        (pmbase + 0x34)
-#define ACPI_ALT_GP_SMI_EN  (pmbase + 0x38)
-#define ACPI_ALT_GP_SMI_STS (pmbase + 0x3A)
-#define ACPI_MON_SMI        (pmbase + 0x40)
-#define ACPI_DEVACT_STS     (pmbase + 0x44)
-#define ACPI_DEVTRAP_EN     (pmbase + 0x48)
-#define ACPI_BUS_ADDR_TRACK (pmbase + 0x4C)
-#define ACPI_BUS_CYC_TRACK  (pmbase + 0x4E)
-
-#define ACPI_PM1a_EVT_BLK ACPI_PM1_STS
-#define ACPI_PM1a_CNT_BLK ACPI_PM1_CNT
-#define ACPI_PM_TMR_BLK   ACPI_PM1_TMR
-#define ACPI_P_BLK        ACPI_PROC_CNT
-#define ACPI_GPE0_BLK     ACPI_GPE0_STS
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
-
-	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
-	memcpy(header->signature, "FACP", 4);
-	header->length = 244;
-	header->revision = 3;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 0;
-
-	fadt->firmware_ctrl = (unsigned long) facs;
-	fadt->dsdt = (unsigned long) dsdt;
-	fadt->preferred_pm_profile = 7; /* Performance Server */
-	fadt->sci_int = 0x9;
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
-	fadt->smi_cmd = APM_CNT;
-#else
-	fadt->smi_cmd = 0x00;
-#endif
-	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
-	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0xe2;
-
-	fadt->pm1a_evt_blk = pmbase;
-	fadt->pm1b_evt_blk = 0x0;
-	fadt->pm1a_cnt_blk = pmbase + 0x4;
-	fadt->pm1b_cnt_blk = 0x0;
-	fadt->pm2_cnt_blk = 0x0;
-	fadt->pm_tmr_blk = pmbase + 0x8;
-	fadt->gpe0_blk = pmbase + 0x28;
-	fadt->gpe1_blk = 0x0;
-
-	fadt->pm1_evt_len = 0x4;
-	fadt->pm1_cnt_len = 0x2;
-	fadt->pm2_cnt_len = 0x0;
-	fadt->pm_tmr_len = 0x4;
-	fadt->gpe0_blk_len = 0x8;
-	fadt->gpe1_blk_len = 0x0;
-	fadt->gpe1_base = 0x0;
-	fadt->cst_cnt = 0xe3;
-	fadt->p_lvl2_lat = 0x65;
-	fadt->p_lvl3_lat = 0x3e9;
-	fadt->flush_size = 0x400;
-	fadt->flush_stride = 0x10;
-	fadt->duty_offset = 0x1;
-	fadt->duty_width = 0x3;
-	fadt->day_alrm = 0xd;
-	fadt->mon_alrm = 0x00;
-	fadt->century = 0x00;
-	fadt->iapc_boot_arch = 0x03;
-	fadt->flags = 0xa5;
-
-	fadt->reset_reg.space_id = 1;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0;
-	fadt->reset_value = 6;
-	fadt->res3 = 0;
-	fadt->res4 = 0;
-	fadt->res5 = 0;
-	fadt->x_firmware_ctl_l = (u32)facs;
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (u32)dsdt;
-	fadt->x_dsdt_h = 0;
-
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = pmbase;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 32;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 0;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 0;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = 0x0;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	fadt->x_gpe0_blk.space_id = 1;
-	fadt->x_gpe0_blk.bit_width = 64;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
-	fadt->x_gpe0_blk.addrh = 0x0;
-
-	fadt->x_gpe1_blk.space_id = 1;
-	fadt->x_gpe1_blk.bit_width = 32;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0x0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum =
-	    acpi_checksum((void *) fadt, header->length);
-}
diff --git a/src/mainboard/intel/eagleheights/ioapic.h b/src/mainboard/intel/eagleheights/ioapic.h
deleted file mode 100644
index 82618f665b..0000000000
--- a/src/mainboard/intel/eagleheights/ioapic.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define IOAPIC_I3100 2
-#define INTEL_IOAPIC_NUM_INTERRUPTS 24
diff --git a/src/mainboard/intel/eagleheights/irq_tables.c b/src/mainboard/intel/eagleheights/irq_tables.c
deleted file mode 100644
index 0267d62953..0000000000
--- a/src/mainboard/intel/eagleheights/irq_tables.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,		/* u32 signature */
-	PIRQ_VERSION,		/* u16 version */
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,		/* Max. number of devices on the bus */
-	0x00,			/* Interrupt router bus */
-	(0x1f << 3) | 0x0,	/* Interrupt router dev */
-	0,			/* IRQs devoted exclusively to PCI usage */
-	0x8086,			/* Vendor */
-	0x2670,			/* Device */
-	0,			/* Miniport */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x4b,			/* Checksum (has to be set to some value that
-				 * would give 0 after the sum of all bytes
-				 * for this structure (including checksum).
-				 */
-	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
-		{0x00, (0x03 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
-		{0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
-		{0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0},
-		{0x01, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x1, 0x0},
-		{0x01, (0x01 << 3) | 0x0, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
deleted file mode 100644
index dae3879be3..0000000000
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-// Generate MP-table IRQ numbers for PCI devices.
-#define IO_APIC0 2
-
-#define INT_A	0
-#define INT_B	1
-#define INT_C	2
-#define INT_D	3
-#define PCI_IRQ(dev, intLine)	(((dev)<<2) | intLine)
-
-#define PIRQ_A 16
-#define PIRQ_B 17
-#define PIRQ_C 18
-#define PIRQ_D 19
-#define PIRQ_E 20
-#define PIRQ_F 21
-#define PIRQ_G 22
-#define PIRQ_H 23
-
-// RCBA
-#define RCBA 0xF0
-
-#define RCBA_D31IP 0x3100
-#define RCBA_D30IP 0x3104
-#define RCBA_D29IP 0x3108
-#define RCBA_D28IP 0x310C
-#define RCBA_D31IR 0x3140
-#define RCBA_D30IR 0x3142
-#define RCBA_D29IR 0x3144
-#define RCBA_D28IR 0x3146
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	unsigned char bus_chipset, bus_pci;
-	unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b;
-	int bus_isa, i;
-	uint32_t pin, route;
-	device_t dev;
-	struct resource *res;
-	u8 *rcba;
-
-	dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
-	res = find_resource(dev, RCBA);
-	if (!res) {
-		return NULL;
-	}
-	rcba = res2mmio(res, 0, 0);
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-
-	/* Get bus numbers */
-	bus_chipset = 0;
-
-	/* PCI */
-	dev = dev_find_slot(0, PCI_DEVFN(0x1E,0));
-	if (dev) {
-		bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	} else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
-		bus_pci = 6;
-	}
-
-	dev = dev_find_slot(0, PCI_DEVFN(2,0));
-	if(dev) {
-		bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	} else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCIe Port A  0:2.0, using defaults\n");
-		bus_pcie_a = 1;
-	}
-
-	dev = dev_find_slot(0, PCI_DEVFN(3,0));
-	if(dev) {
-		bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	} else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
-		bus_pcie_a1 = 2;
-	}
-
-	dev = dev_find_slot(0, PCI_DEVFN(0x1C,0));
-	if(dev) {
-		bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	} else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
-		bus_pcie_b = 3;
-	}
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/*I/O APICs: APIC ID Version State Address*/
-	smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
-
-	mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);
-
-	/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	mptable_lintsrc(mc, bus_isa);
-
-	/* Internal PCI device for i3100 */
-
-	/* EDMA
-	 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(1, INT_A), IO_APIC0, PIRQ_A);
-
-	/* PCIe Port A
-	 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(2, INT_A), IO_APIC0, PIRQ_A);
-
-	/* PCIe Port A1
-	 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(3, INT_A), IO_APIC0, PIRQ_A);
-
-	/* PCIe Port B
-	 */
-	for(i = 0; i < 4; i++) {
-		pin = (read32(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
-		if(pin > 0) {
-			pin -= 1;
-			route = PIRQ_A + ((read16(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);
-		}
-	}
-
-	/* USB 1.1 : device 29, function 0, 1
-	 */
-	for(i = 0; i < 2; i++) {
-		pin = (read32(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
-		if(pin > 0) {
-			 pin -= 1;
-			route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
-		}
-	}
-
-	/* USB 2.0 : device 29, function 7
-	*/
-	pin = (read32(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
-	if(pin > 0) {
-		pin -= 1;
-		route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
-	}
-
-	/* SATA : device 31 function 2
-	 * SMBus : device 31 function 3
-	 * Performance counters : device 31 function 4
-	 */
-	for(i = 2; i < 5; i++) {
-		pin = (read32(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
-		if(pin > 0) {
-			pin -= 1;
-			route = PIRQ_A + ((read16(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);
-		}
-	}
-
-	/* SLOTS */
-
-	/* PCIe 4x slot A
-	 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
-
-	/* PCIe 4x slot A1
-	 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
-
-	/* PCIe 4x slot B
-	 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
-
-	/* PCI slot
-	 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
-
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
deleted file mode 100644
index 21313eb491..0000000000
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <delay.h>
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include <cpu/intel/speedstep.h>
-#include "southbridge/intel/i3100/early_smbus.c"
-#include "southbridge/intel/i3100/early_lpc.c"
-#include "southbridge/intel/i3100/reset.c"
-#include <superio/intel/i3100/i3100.h>
-#include <superio/smsc/smscsuperio/smscsuperio.h>
-#include <northbridge/intel/i3100/i3100.h>
-#include <southbridge/intel/i3100/i3100.h>
-#include "lib/debug.c" // XXX
-
-#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
-#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
-
-#define RCBA_RPC   0x0224 /* 32 bit */
-
-#define RCBA_TCTL  0x3000 /*  8 bit */
-
-#define RCBA_D31IP 0x3100 /* 32 bit */
-#define RCBA_D30IP 0x3104 /* 32 bit */
-#define RCBA_D29IP 0x3108 /* 32 bit */
-#define RCBA_D28IP 0x310C /* 32 bit */
-#define RCBA_D31IR 0x3140 /* 16 bit */
-#define RCBA_D30IR 0x3142 /* 16 bit */
-#define RCBA_D29IR 0x3144 /* 16 bit */
-#define RCBA_D28IR 0x3146 /* 16 bit */
-
-#define RCBA_RTC   0x3400 /* 32 bit */
-#define RCBA_HPTC  0x3404 /* 32 bit */
-#define RCBA_GCS   0x3410 /* 32 bit */
-#define RCBA_BUC   0x3414 /*  8 bit */
-#define RCBA_FD    0x3418 /* 32 bit */
-#define RCBA_PRC   0x341C /* 32 bit */
-
-static inline int spd_read_byte(u16 device, u8 address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include <northbridge/intel/i3100/raminit.h>
-#include "northbridge/intel/i3100/memory_initialized.c"
-#include "northbridge/intel/i3100/raminit.c"
-#include "lib/generic_sdram.c"
-#include "northbridge/intel/i3100/reset_test.c"
-#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
-
-static void early_config(void)
-{
-	u32 gcs, rpc, fd;
-
-	/* Enable RCBA */
-	pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-
-	/* Disable watchdog */
-	gcs = read32(DEFAULT_RCBA + RCBA_GCS);
-	gcs |= (1 << 5); /* No reset */
-	write32(DEFAULT_RCBA + RCBA_GCS, gcs);
-
-	/* Configure PCIe port B as 4x */
-	rpc = read32(DEFAULT_RCBA + RCBA_RPC);
-	rpc |= (3 << 0);
-	write32(DEFAULT_RCBA + RCBA_RPC, rpc);
-
-	/* Disable Modem, Audio, PCIe ports 2/3/4 */
-	fd = read32(DEFAULT_RCBA + RCBA_FD);
-	fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
-	write32(DEFAULT_RCBA + RCBA_FD, fd);
-
-	/* Enable HPET */
-	write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
-
-	/* Improve interrupt routing
-	 * D31:F2 SATA        INTB# -> PIRQD
-	 * D31:F3 SMBUS       INTB# -> PIRQD
-	 * D31:F4 CHAP        INTD# -> PIRQA
-	 * D29:F0 USB1#1      INTA# -> PIRQH
-	 * D29:F1 USB1#2      INTB# -> PIRQD
-	 * D29:F7 USB2        INTA# -> PIRQH
-	 * D28:F0 PCIe Port 1 INTA# -> PIRQE
-	 */
-
-	write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230);
-	write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210);
-	write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237);
-	write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214);
-
-	/* Setup sata mode */
-	pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
-	/* int boot_mode = 0; */
-
-	static const struct mem_controller mch[] = {
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x00, 0),
-			.f1 = PCI_DEV(0, 0x00, 1),
-			.f2 = PCI_DEV(0, 0x00, 2),
-			.f3 = PCI_DEV(0, 0x00, 3),
-			.channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
-			.channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
-		}
-	};
-
-	if (bist == 0)
-		enable_lapic();
-
-	/* Setup the console */
-	i3100_enable_superio();
-	i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
-
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	/* Perform early board specific init */
-	early_config();
-
-	/* Prevent the TCO timer from rebooting us */
-	i3100_halt_tco_timer();
-
-	/* Enable SPD ROMs and DDR-II DRAM */
-	enable_smbus();
-
-	/* Enable SpeedStep and automatic thermal throttling */
-	{
-		msr_t msr;
-		u16 perf;
-
-		msr = rdmsr(IA32_MISC_ENABLES);
-		msr.lo |= (1 << 3) | (1 << 16);
-		wrmsr(IA32_MISC_ENABLES, msr);
-
-		/* Set CPU frequency/voltage to maximum */
-
-		/* Read performance status register and keep
-		 * bits 47:32, where BUS_RATIO_MAX and VID_MAX
-		 * are encoded
-		 */
-		msr = rdmsr(IA32_PERF_STATUS);
-		perf = msr.hi & 0x0000ffff;
-
-		/* Write VID_MAX & BUS_RATIO_MAX to
-		 * performance control register
-		 */
-		msr = rdmsr(IA32_PERF_CTL);
-		msr.lo &= 0xffff0000;
-		msr.lo |= perf;
-		wrmsr(IA32_PERF_CTL, msr);
-	}
-
-	/* Initialize memory */
-	sdram_initialize(ARRAY_SIZE(mch), mch);
-}
diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig
deleted file mode 100644
index 11c26261c9..0000000000
--- a/src/mainboard/intel/mtarvon/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-if BOARD_INTEL_MTARVON
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_INTEL_SOCKET_MPGA479M
-	select NORTHBRIDGE_INTEL_I3100
-	select SOUTHBRIDGE_INTEL_I3100
-	select SUPERIO_INTEL_I3100
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select BOARD_ROMSIZE_KB_2048
-
-config MAINBOARD_DIR
-	string
-	default intel/mtarvon
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "3100 devkit (Mt. Arvon)"
-
-config IRQ_SLOT_COUNT
-	int
-	default 1
-
-config MAX_CPUS
-	int
-	default 4
-
-endif # BOARD_INTEL_MTARVON
diff --git a/src/mainboard/intel/mtarvon/Kconfig.name b/src/mainboard/intel/mtarvon/Kconfig.name
deleted file mode 100644
index 30b547e28f..0000000000
--- a/src/mainboard/intel/mtarvon/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_INTEL_MTARVON
-	bool "3100 devkit (Mt. Arvon)"
diff --git a/src/mainboard/intel/mtarvon/board_info.txt b/src/mainboard/intel/mtarvon/board_info.txt
deleted file mode 100644
index b351b8e696..0000000000
--- a/src/mainboard/intel/mtarvon/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: eval
diff --git a/src/mainboard/intel/mtarvon/devicetree.cb b/src/mainboard/intel/mtarvon/devicetree.cb
deleted file mode 100644
index c1ff1d585a..0000000000
--- a/src/mainboard/intel/mtarvon/devicetree.cb
+++ /dev/null
@@ -1,45 +0,0 @@
-chip northbridge/intel/i3100
-        device domain 0 on
-                subsystemid 0x8086 0x2680 inherit
-                device pci 00.0 on end # IMCH
-                device pci 00.1 on end # IMCH error status
-                device pci 01.0 on end # IMCH EDMA engine
-                device pci 02.0 on end # PCIe port A/A0
-                device pci 03.0 on end # PCIe port A1
-                chip southbridge/intel/i3100
-                        # PIRQ line -> legacy IRQ mappings
-                        register "pirq_a_d" = "0x0b070a05"
-                        register "pirq_e_h" = "0x0a808080"
-
-                        device pci 1c.0 on end # PCIe port B0
-                        device pci 1c.1 on end # PCIe port B1
-                        device pci 1c.2 on end # PCIe port B2
-                        device pci 1c.3 on end # PCIe port B3
-                        device pci 1d.0 on end # USB (UHCI) 1
-                        device pci 1d.1 on end # USB (UHCI) 2
-                        device pci 1d.7 on end # USB (EHCI)
-                        device pci 1e.0 on end # PCI bridge
-                        device pci 1e.2 on end # audio
-                        device pci 1e.3 on end # modem
-                        device pci 1f.0 on     # LPC bridge
-                                chip superio/intel/i3100
-                                        device pnp 4e.4 on # Com1
-                                                 io 0x60 = 0x3f8
-                                                irq 0x70 = 4
-                                        end
-                                        device pnp 4e.5 on # Com2
-                                                 io 0x60 = 0x2f8
-                                                irq 0x70 = 3
-                                        end
-                                end
-                        end
-                        device pci 1f.2 on end # SATA
-                        device pci 1f.3 on end # SMBus
-                end
-        end
-        device cpu_cluster 0 on
-                chip cpu/intel/socket_mPGA479M
-                        device lapic 0 on end
-                end
-        end
-end
diff --git a/src/mainboard/intel/mtarvon/irq_tables.c b/src/mainboard/intel/mtarvon/irq_tables.c
deleted file mode 100644
index 958b2d389b..0000000000
--- a/src/mainboard/intel/mtarvon/irq_tables.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE, /* u32 signature */
-	PIRQ_VERSION,   /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices)  */
-	0x00,       /* u8 Bus 0 */
-	(0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */
-	0x0000,     /* u16 reserve IRQ for PCI */
-	0x8086,     /* u16 Vendor */
-	0x2670,     /* Device ID */
-	0x00000000, /* u32 miniport_data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x49,   /*  u8 checksum - mod 256 checksum must give zero */
-	{  /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu  */
-	    {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00,  0x00},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
deleted file mode 100644
index ee9d1c28f2..0000000000
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* This code is based on src/mainboard/intel/jarrell/mptable.c */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-	u8 bus_pci = 6;
-	u8 bus_pcie_a = 1;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/* IOAPIC handling */
-	smp_write_ioapic(mc, 0x01, 0x20, VIO_APIC_VADDR);
-
-	mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);
-
-	/* Standard local interrupt assignments */
-	mptable_lintsrc(mc, bus_isa);
-
-	/* Internal PCI devices */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x01 << 2)|0, 0x01, 0x10); /* DMA controller */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x02 << 2)|0, 0x01, 0x10); /* PCIe port A */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x03 << 2)|0, 0x01, 0x10); /* PCIe port A1 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1c << 2)|0, 0x01, 0x10); /* PCIe port B0 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1c << 2)|1, 0x01, 0x11); /* PCIe port B1 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1c << 2)|2, 0x01, 0x12); /* PCIe port B2 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1c << 2)|3, 0x01, 0x13); /* PCIe port B3 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1d << 2)|0, 0x01, 0x10); /* UHCI0/EHCI */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1d << 2)|1, 0x01, 0x11); /* UHCI1 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1e << 2)|0, 0x01, 0x10); /* Audio */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1e << 2)|1, 0x01, 0x11); /* Modem */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1f << 2)|1, 0x01, 0x11); /* SATA/SMBus */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1f << 2)|3, 0x01, 0x13); /* ? */
-
-	/* PCI slot */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_pci, 0x00, 0x01, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_pci, 0x01, 0x01, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_pci, 0x02, 0x01, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_pci, 0x03, 0x01, 0x13);
-
-	/* PCIe port A slot */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_pcie_a, 0x00, 0x01, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_pcie_a, 0x01, 0x01, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_pcie_a, 0x02, 0x01, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_pcie_a, 0x03, 0x01, 0x13);
-
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
deleted file mode 100644
index 13f425e1cf..0000000000
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include "southbridge/intel/i3100/early_smbus.c"
-#include "southbridge/intel/i3100/early_lpc.c"
-#include <northbridge/intel/i3100/raminit.h>
-#include <superio/intel/i3100/i3100.h>
-#include "northbridge/intel/i3100/memory_initialized.c"
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include <spd.h>
-
-#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0)
-#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
-
-#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
-
-static inline int spd_read_byte(u16 device, u8 address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i3100/raminit.c"
-#include "lib/generic_sdram.c"
-#if 0 /* skip_romstage doesn't compile with gcc */
-#include "arch/x86/lib/stages.c"
-#endif
-
-void mainboard_romstage_entry(unsigned long bist)
-{
-	msr_t msr;
-	u16 perf;
-	static const struct mem_controller mch[] = {
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x00, 0),
-			.f1 = PCI_DEV(0, 0x00, 1),
-			.f2 = PCI_DEV(0, 0x00, 2),
-			.f3 = PCI_DEV(0, 0x00, 3),
-			.channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
-			.channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
-		}
-	};
-
-	if (bist == 0) {
-#if 0 /* skip_romstage doesn't compile with gcc */
-		/* Skip this if there was a built in self test failure */
-		if (memory_initialized()) {
-			skip_romstage();
-		}
-#endif
-	}
-
-	/* Set up the console */
-	i3100_enable_superio();
-	i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
-
-	console_init();
-
-	/* Prevent the TCO timer from rebooting us */
-	i3100_halt_tco_timer();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	/* print_pci_devices(); */
-	enable_smbus();
-	/* dump_spd_registers(); */
-
-	/* Enable SpeedStep and automatic thermal throttling */
-	/* FIXME: move to Pentium M init code */
-	msr = rdmsr(0x1a0);
-	msr.lo |= (1 << 3) | (1 << 16);
-	wrmsr(0x1a0, msr);
-	msr = rdmsr(0x19d);
-	msr.lo |= (1 << 16);
-	wrmsr(0x19d, msr);
-
-	/* Set CPU frequency/voltage to maximum */
-	/* FIXME: move to Pentium M init code */
-	msr = rdmsr(IA32_PERF_STATUS);
-	perf = msr.hi & 0xffff;
-	msr = rdmsr(0x199);
-	msr.lo &= 0xffff0000;
-	msr.lo |= perf;
-	wrmsr(0x199, msr);
-
-	sdram_initialize(ARRAY_SIZE(mch), mch);
-	/* dump_pci_devices(); */
-	/* dump_pci_device(PCI_DEV(0, 0x00, 0)); */
-	/* dump_bar14(PCI_DEV(0, 0x00, 0)); */
-}
diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig
deleted file mode 100644
index cd8e478f1b..0000000000
--- a/src/mainboard/intel/truxton/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-if BOARD_INTEL_TRUXTON
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_INTEL_EP80579
-	select NORTHBRIDGE_INTEL_I3100
-	select SOUTHBRIDGE_INTEL_I3100
-	select SUPERIO_INTEL_I3100
-	select SUPERIO_SMSC_SMSCSUPERIO
-	select HAVE_HARD_RESET
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select BOARD_ROMSIZE_KB_2048
-
-config MAINBOARD_DIR
-	string
-	default intel/truxton
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Truxton"
-
-config IRQ_SLOT_COUNT
-	int
-	default 1
-
-config MAX_CPUS
-	int
-	default 4
-
-endif # BOARD_INTEL_TRUXTON
diff --git a/src/mainboard/intel/truxton/Kconfig.name b/src/mainboard/intel/truxton/Kconfig.name
deleted file mode 100644
index f91b44538f..0000000000
--- a/src/mainboard/intel/truxton/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_INTEL_TRUXTON
-	bool "EP80579 devkit (Truxton)"
diff --git a/src/mainboard/intel/truxton/Makefile.inc b/src/mainboard/intel/truxton/Makefile.inc
deleted file mode 100644
index 6ef4fc9d50..0000000000
--- a/src/mainboard/intel/truxton/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2
diff --git a/src/mainboard/intel/truxton/board_info.txt b/src/mainboard/intel/truxton/board_info.txt
deleted file mode 100644
index 5ae0fde757..0000000000
--- a/src/mainboard/intel/truxton/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Board name: EP80579 devkit (Truxton)
-Category: eval
-Release year: 2009
diff --git a/src/mainboard/intel/truxton/devicetree.cb b/src/mainboard/intel/truxton/devicetree.cb
deleted file mode 100644
index 05fb05ecf1..0000000000
--- a/src/mainboard/intel/truxton/devicetree.cb
+++ /dev/null
@@ -1,55 +0,0 @@
-chip northbridge/intel/i3100
-        device domain 0 on
-                subsystemid 0x8086 0x2680 inherit
-                device pci 00.0 on end # IMCH
-                device pci 00.1 on end # IMCH error status
-                device pci 01.0 on end # IMCH EDMA engine
-                device pci 02.0 on end # PCIe port A/A0
-                device pci 03.0 on end # PCIe port A1
-                device pci 04.0 on end # ?
-                device pci 08.0 off end # must be off to boot
-                device pci 0d.0 off end # must be off to boot
-                device pci 0d.1 off end # must be off to boot
-                chip southbridge/intel/i3100
-                        # PIRQ line -> legacy IRQ mappings
-                        register "pirq_a_d" = "0x0b070a05"
-                        register "pirq_e_h" = "0x0a808080"
-
-                        device pci 1d.0 on end  # USB (UHCI)
-                        device pci 1d.7 on end  # USB (EHCI)
-                        device pci 1f.0 on      # LPC bridge
-                                chip superio/intel/i3100
-                                        device pnp 4e.4 on # Com1
-                                                 io 0x60 = 0x3f8
-                                                irq 0x70 = 4
-                                        end
-                                        device pnp 4e.5 on # Com2
-                                                 io 0x60 = 0x2f8
-                                                irq 0x70 = 3
-                                        end
-				end
-				chip superio/smsc/smscsuperio
-					device pnp 2e.0 off end
-					device pnp 2e.3 off end
-					device pnp 2e.4 off end
-					device pnp 2e.5 off end
-					device pnp 2e.7 on # PS/2 keyboard / mouse
-            					io 0x60 = 0x60
-            					io 0x62 = 0x64
-            					irq 0x70 = 1	# PS/2 keyboard interrupt
-            					irq 0x72 = 12	# PS/2 mouse interrupt
-					end
-					device pnp 2e.a off end
-                                end
-                        end
-                        device pci 1f.2 on end  # SATA
-                        device pci 1f.3 on end  # SMBus
-                        device pci 1f.4 on end  # ?
-                end
-        end
-        device cpu_cluster 0 on
-                chip cpu/intel/ep80579
-                        device lapic 0 on end
-                end
-        end
-end
diff --git a/src/mainboard/intel/truxton/irq_tables.c b/src/mainboard/intel/truxton/irq_tables.c
deleted file mode 100644
index c34809f677..0000000000
--- a/src/mainboard/intel/truxton/irq_tables.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE, /* u32 signature */
-	PIRQ_VERSION,   /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices)  */
-	0x00,       /* u8 Bus 0 */
-	(0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */
-	0x0000,     /* u16 reserve IRQ for PCI */
-	0x8086,     /* u16 Vendor */
-	0x5031,     /* Device ID */
-	0x00000000, /* u32 miniport_data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x5e,   /*  u8 checksum - mod 256 checksum must give zero */
-	{  /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu  */
-	    {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00,  0x00},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
deleted file mode 100644
index ca934b3aee..0000000000
--- a/src/mainboard/intel/truxton/mptable.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-	u8 bus_pea0 = 0;
-	u8 bus_pea1 = 0;
-	u8 bus_aioc;
-	device_t dev;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-
-	/* AIOC bridge */
-	dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
-	if (dev) {
-		bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	}
-	else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
-		bus_aioc = 0;
-	}
-	/* PCIe A0 */
-	dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
-	if (dev) {
-		bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	}
-	else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n");
-		bus_pea0 = 0;
-	}
-	/* PCIe A1 */
-	dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
-	if (dev) {
-		bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	}
-	else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n");
-		bus_pea1 = 0;
-	}
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/* IOAPIC handling */
-	smp_write_ioapic(mc, 0x8, 0x20, VIO_APIC_VADDR);
-
-	mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
-
-	/* Standard local interrupt assignments */
-	mptable_lintsrc(mc, bus_isa);
-
-	/* IMCH/IICH PCI devices */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x01 << 2)|0, 0x8, 0x10); /* DMA controller */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x02 << 2)|0, 0x8, 0x10); /* PCIe port A bridge */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x03 << 2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x04 << 2)|0, 0x8, 0x10); /* AIOC PCI bridge */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1d << 2)|0, 0x8, 0x10); /* UHCI/EHCI */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1f << 2)|1, 0x8, 0x11); /* SATA/SMBus */
-
-	if (bus_pea0) {
-		/* PCIe slot 0 */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea0, (0 << 2)|0, 0x8, 0x10);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea0, (0 << 2)|1, 0x8, 0x11);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea0, (0 << 2)|2, 0x8, 0x12);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea0, (0 << 2)|3, 0x8, 0x13);
-	}
-
-	if (bus_pea1) {
-		/* PCIe slots 1-4 */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea1, (0 << 2)|0, 0x8, 0x10);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea1, (0 << 2)|1, 0x8, 0x11);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea1, (0 << 2)|2, 0x8, 0x12);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea1, (0 << 2)|3, 0x8, 0x13);
-	}
-
-	if (bus_aioc) {
-		/* AIOC PCI devices */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_aioc, (0 << 2)|0, 0x8, 0x10); /* GbE0 */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_aioc, (1 << 2)|0, 0x8, 0x11); /* GbE1 */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_aioc, (2 << 2)|0, 0x8, 0x12); /* GbE2 */
-	}
-
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
deleted file mode 100644
index 4b64210c38..0000000000
--- a/src/mainboard/intel/truxton/romstage.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include "southbridge/intel/i3100/early_smbus.c"
-#include "southbridge/intel/i3100/early_lpc.c"
-#include <northbridge/intel/i3100/raminit_ep80579.h>
-#include <superio/intel/i3100/i3100.h>
-#include "lib/debug.c" // XXX
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include <spd.h>
-
-#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
-
-static inline int spd_read_byte(u16 device, u8 address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i3100/raminit_ep80579.c"
-#include "lib/generic_sdram.c"
-
-#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
-
-void mainboard_romstage_entry(unsigned long bist)
-{
-	static const struct mem_controller mch[] = {
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x00, 0),
-			.channel0 = { DIMM2, DIMM3 },
-		}
-	};
-
-	if (bist == 0) {
-		/* Skip this if there was a built in self test failure */
-		if (memory_initialized())
-			return;
-	}
-
-	/* Set up the console */
-	i3100_enable_superio();
-	i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
-
-	console_init();
-
-	/* Prevent the TCO timer from rebooting us */
-	i3100_halt_tco_timer();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-#ifdef TRUXTON_DEBUG
-	print_pci_devices();
-#endif
-	enable_smbus();
-
-	sdram_initialize(ARRAY_SIZE(mch), mch);
-	dump_pci_devices();
-	dump_pci_device(PCI_DEV(0, 0x00, 0));
-#ifdef TRUXTON_DEBUG
-	dump_bar14(PCI_DEV(0, 0x00, 0));
-#endif
-}