diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2016-02-06 18:07:59 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-23 00:28:06 +0100 |
| commit | 273a8dca1f7896c73b812ecc2c6cd2572ac51d6a (patch) | |
| tree | a086a9e33bcef9c6490c6cc706a5aef79651f3b5 /src/mainboard/intel | |
| parent | 9a4881a783fa1edc730dc484bb2c293d92e45823 (diff) | |
| download | coreboot-273a8dca1f7896c73b812ecc2c6cd2572ac51d6a.tar.xz | |
southbridge/intel/lynxpoint: Use common gpio.c
Use shared gpio code from common folder, except for
INTEL_LYNXPOINT_LP, which has it's own gpio code.
Needs test on real hardware !
Change-Id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13615
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/baskingridge/chromeos.c | 24 | ||||
| -rw-r--r-- | src/mainboard/intel/baskingridge/gpio.h | 2 |
2 files changed, 4 insertions, 22 deletions
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 3885257851..94e8d89a06 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -19,7 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/gpio.h> +#include <southbridge/intel/common/gpio.h> #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -82,38 +82,20 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_developer_mode_switch(void) { - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 0); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); -#endif - u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; - u32 gp_lvl2 = inl(gpio_base + GP_LVL2); - /* * Developer: GPIO48, Connected to J8E4, however the silkscreen says * J8E3. The jumper is active low. */ - return !((gp_lvl2 >> (48-32)) & 1); + return !get_gpio(48); } int get_recovery_mode_switch(void) { - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 0); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); -#endif - u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; - u32 gp_lvl3 = inl(gpio_base + GP_LVL3); - /* * Recovery: GPIO69, Connected to J8E3, however the silkscreen says * J8E2. The jump is active high. */ - return (gp_lvl3 >> (69-64)) & 1; + return get_gpio(69); } int get_write_protect_state(void) diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.h index 99bec38886..f2be9e3c84 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.h @@ -16,7 +16,7 @@ #ifndef BASKING_RIDGE_GPIO_H #define BASKING_RIDGE_GPIO_H -#include "southbridge/intel/lynxpoint/gpio.h" +#include <southbridge/intel/common/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* PCH_GPIO0_R -> S_GPIO -> J9F4 */ |