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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 18:11:03 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:47:58 +0000 |
| commit | 360d94745feea766de7ef19487ba9158221faca0 (patch) | |
| tree | 757402cd145f8f791cfa9594570e4d2a5d5f026c /src/mainboard/intel | |
| parent | 67d59d1756423a96aca5249b59c4e3759b2f3721 (diff) | |
| download | coreboot-360d94745feea766de7ef19487ba9158221faca0.tar.xz | |
nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCK
There is some overlap between romstage and bootblock.
LPC setup and BAR initialization is now done twice.
The rationale is that the romstage should not depend too
much on the bootblock, since it can reside in a RO fmap
region.
Enabling the console will be done in a followup patch.
Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/dcp847ske/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/Makefile.inc | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index 96bac06a0a..ec86d8455d 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -1,4 +1,5 @@ romstage-y += early_southbridge.c +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-y += smihandler.c diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index b3bf53f028..974241dcc2 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -15,4 +15,5 @@ romstage-y += chromeos.c ramstage-y += chromeos.c +bootblock-y += gpio.c romstage-y += gpio.c |